1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * They are roughly ordered as: 6*4882a593Smuzhiyun * - external clocks 7*4882a593Smuzhiyun * - PLLs 8*4882a593Smuzhiyun * - muxes/dividers in the order they appear in the jz4740 programmers manual 9*4882a593Smuzhiyun * - gates in order of their bit in the CLKGR* registers 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 13*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define JZ4740_CLK_EXT 0 16*4882a593Smuzhiyun #define JZ4740_CLK_RTC 1 17*4882a593Smuzhiyun #define JZ4740_CLK_PLL 2 18*4882a593Smuzhiyun #define JZ4740_CLK_PLL_HALF 3 19*4882a593Smuzhiyun #define JZ4740_CLK_CCLK 4 20*4882a593Smuzhiyun #define JZ4740_CLK_HCLK 5 21*4882a593Smuzhiyun #define JZ4740_CLK_PCLK 6 22*4882a593Smuzhiyun #define JZ4740_CLK_MCLK 7 23*4882a593Smuzhiyun #define JZ4740_CLK_LCD 8 24*4882a593Smuzhiyun #define JZ4740_CLK_LCD_PCLK 9 25*4882a593Smuzhiyun #define JZ4740_CLK_I2S 10 26*4882a593Smuzhiyun #define JZ4740_CLK_SPI 11 27*4882a593Smuzhiyun #define JZ4740_CLK_MMC 12 28*4882a593Smuzhiyun #define JZ4740_CLK_UHC 13 29*4882a593Smuzhiyun #define JZ4740_CLK_UDC 14 30*4882a593Smuzhiyun #define JZ4740_CLK_UART0 15 31*4882a593Smuzhiyun #define JZ4740_CLK_UART1 16 32*4882a593Smuzhiyun #define JZ4740_CLK_DMA 17 33*4882a593Smuzhiyun #define JZ4740_CLK_IPU 18 34*4882a593Smuzhiyun #define JZ4740_CLK_ADC 19 35*4882a593Smuzhiyun #define JZ4740_CLK_I2C 20 36*4882a593Smuzhiyun #define JZ4740_CLK_AIC 21 37*4882a593Smuzhiyun #define JZ4740_CLK_TCU 22 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ 40