1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX8MQ_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define IMX8MQ_CLK_DUMMY 0 11*4882a593Smuzhiyun #define IMX8MQ_CLK_32K 1 12*4882a593Smuzhiyun #define IMX8MQ_CLK_25M 2 13*4882a593Smuzhiyun #define IMX8MQ_CLK_27M 3 14*4882a593Smuzhiyun #define IMX8MQ_CLK_EXT1 4 15*4882a593Smuzhiyun #define IMX8MQ_CLK_EXT2 5 16*4882a593Smuzhiyun #define IMX8MQ_CLK_EXT3 6 17*4882a593Smuzhiyun #define IMX8MQ_CLK_EXT4 7 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* ANAMIX PLL clocks */ 20*4882a593Smuzhiyun /* FRAC PLLs */ 21*4882a593Smuzhiyun /* ARM PLL */ 22*4882a593Smuzhiyun #define IMX8MQ_ARM_PLL_REF_SEL 8 23*4882a593Smuzhiyun #define IMX8MQ_ARM_PLL_REF_DIV 9 24*4882a593Smuzhiyun #define IMX8MQ_ARM_PLL 10 25*4882a593Smuzhiyun #define IMX8MQ_ARM_PLL_BYPASS 11 26*4882a593Smuzhiyun #define IMX8MQ_ARM_PLL_OUT 12 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* GPU PLL */ 29*4882a593Smuzhiyun #define IMX8MQ_GPU_PLL_REF_SEL 13 30*4882a593Smuzhiyun #define IMX8MQ_GPU_PLL_REF_DIV 14 31*4882a593Smuzhiyun #define IMX8MQ_GPU_PLL 15 32*4882a593Smuzhiyun #define IMX8MQ_GPU_PLL_BYPASS 16 33*4882a593Smuzhiyun #define IMX8MQ_GPU_PLL_OUT 17 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* VPU PLL */ 36*4882a593Smuzhiyun #define IMX8MQ_VPU_PLL_REF_SEL 18 37*4882a593Smuzhiyun #define IMX8MQ_VPU_PLL_REF_DIV 19 38*4882a593Smuzhiyun #define IMX8MQ_VPU_PLL 20 39*4882a593Smuzhiyun #define IMX8MQ_VPU_PLL_BYPASS 21 40*4882a593Smuzhiyun #define IMX8MQ_VPU_PLL_OUT 22 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* AUDIO PLL1 */ 43*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL1_REF_SEL 23 44*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL1_REF_DIV 24 45*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL1 25 46*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL1_BYPASS 26 47*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL1_OUT 27 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* AUDIO PLL2 */ 50*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL2_REF_SEL 28 51*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL2_REF_DIV 29 52*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL2 30 53*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL2_BYPASS 31 54*4882a593Smuzhiyun #define IMX8MQ_AUDIO_PLL2_OUT 32 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* VIDEO PLL1 */ 57*4882a593Smuzhiyun #define IMX8MQ_VIDEO_PLL1_REF_SEL 33 58*4882a593Smuzhiyun #define IMX8MQ_VIDEO_PLL1_REF_DIV 34 59*4882a593Smuzhiyun #define IMX8MQ_VIDEO_PLL1 35 60*4882a593Smuzhiyun #define IMX8MQ_VIDEO_PLL1_BYPASS 36 61*4882a593Smuzhiyun #define IMX8MQ_VIDEO_PLL1_OUT 37 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* SYS1 PLL */ 64*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL1_REF_SEL 38 65*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL1_REF_DIV 39 66*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL1 40 67*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL1_OUT 41 68*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL1_OUT_DIV 42 69*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL2 43 70*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL2_DIV 44 71*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL2_OUT 45 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* SYS2 PLL */ 74*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL1_REF_SEL 46 75*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL1_REF_DIV 47 76*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL1 48 77*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL1_OUT 49 78*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL1_OUT_DIV 50 79*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL2 51 80*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL2_DIV 52 81*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL2_OUT 53 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* SYS3 PLL */ 84*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL1_REF_SEL 54 85*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL1_REF_DIV 55 86*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL1 56 87*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL1_OUT 57 88*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL1_OUT_DIV 58 89*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL2 59 90*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL2_DIV 60 91*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL2_OUT 61 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* DRAM PLL */ 94*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL1_REF_SEL 62 95*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL1_REF_DIV 63 96*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL1 64 97*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL1_OUT 65 98*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL1_OUT_DIV 66 99*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL2 67 100*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL2_DIV 68 101*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL2_OUT 69 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* SYS PLL DIV */ 104*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_40M 70 105*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_80M 71 106*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_100M 72 107*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_133M 73 108*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_160M 74 109*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_200M 75 110*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_266M 76 111*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_400M 77 112*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_800M 78 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_50M 79 115*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_100M 80 116*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_125M 81 117*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_166M 82 118*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_200M 83 119*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_250M 84 120*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_333M 85 121*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_500M 86 122*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_1000M 87 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* CCM ROOT clocks */ 125*4882a593Smuzhiyun /* A53 */ 126*4882a593Smuzhiyun #define IMX8MQ_CLK_A53_SRC 88 127*4882a593Smuzhiyun #define IMX8MQ_CLK_A53_CG 89 128*4882a593Smuzhiyun #define IMX8MQ_CLK_A53_DIV 90 129*4882a593Smuzhiyun /* M4 */ 130*4882a593Smuzhiyun #define IMX8MQ_CLK_M4_SRC 91 131*4882a593Smuzhiyun #define IMX8MQ_CLK_M4_CG 92 132*4882a593Smuzhiyun #define IMX8MQ_CLK_M4_DIV 93 133*4882a593Smuzhiyun /* VPU */ 134*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_SRC 94 135*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_CG 95 136*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_DIV 96 137*4882a593Smuzhiyun /* GPU CORE */ 138*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_CORE_SRC 97 139*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_CORE_CG 98 140*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_CORE_DIV 99 141*4882a593Smuzhiyun /* GPU SHADER */ 142*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_SHADER_SRC 100 143*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_SHADER_CG 101 144*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_SHADER_DIV 102 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* BUS TYPE */ 147*4882a593Smuzhiyun /* MAIN AXI */ 148*4882a593Smuzhiyun #define IMX8MQ_CLK_MAIN_AXI 103 149*4882a593Smuzhiyun /* ENET AXI */ 150*4882a593Smuzhiyun #define IMX8MQ_CLK_ENET_AXI 104 151*4882a593Smuzhiyun /* NAND_USDHC_BUS */ 152*4882a593Smuzhiyun #define IMX8MQ_CLK_NAND_USDHC_BUS 105 153*4882a593Smuzhiyun /* VPU BUS */ 154*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_BUS 106 155*4882a593Smuzhiyun /* DISP_AXI */ 156*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_AXI 107 157*4882a593Smuzhiyun /* DISP APB */ 158*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_APB 108 159*4882a593Smuzhiyun /* DISP RTRM */ 160*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_RTRM 109 161*4882a593Smuzhiyun /* USB_BUS */ 162*4882a593Smuzhiyun #define IMX8MQ_CLK_USB_BUS 110 163*4882a593Smuzhiyun /* GPU_AXI */ 164*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_AXI 111 165*4882a593Smuzhiyun /* GPU_AHB */ 166*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_AHB 112 167*4882a593Smuzhiyun /* NOC */ 168*4882a593Smuzhiyun #define IMX8MQ_CLK_NOC 113 169*4882a593Smuzhiyun /* NOC_APB */ 170*4882a593Smuzhiyun #define IMX8MQ_CLK_NOC_APB 115 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* AHB */ 173*4882a593Smuzhiyun #define IMX8MQ_CLK_AHB 116 174*4882a593Smuzhiyun /* AUDIO AHB */ 175*4882a593Smuzhiyun #define IMX8MQ_CLK_AUDIO_AHB 117 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* DRAM_ALT */ 178*4882a593Smuzhiyun #define IMX8MQ_CLK_DRAM_ALT 118 179*4882a593Smuzhiyun /* DRAM APB */ 180*4882a593Smuzhiyun #define IMX8MQ_CLK_DRAM_APB 119 181*4882a593Smuzhiyun /* VPU_G1 */ 182*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_G1 120 183*4882a593Smuzhiyun /* VPU_G2 */ 184*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_G2 121 185*4882a593Smuzhiyun /* DISP_DTRC */ 186*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_DTRC 122 187*4882a593Smuzhiyun /* DISP_DC8000 */ 188*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_DC8000 123 189*4882a593Smuzhiyun /* PCIE_CTRL */ 190*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE1_CTRL 124 191*4882a593Smuzhiyun /* PCIE_PHY */ 192*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE1_PHY 125 193*4882a593Smuzhiyun /* PCIE_AUX */ 194*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE1_AUX 126 195*4882a593Smuzhiyun /* DC_PIXEL */ 196*4882a593Smuzhiyun #define IMX8MQ_CLK_DC_PIXEL 127 197*4882a593Smuzhiyun /* LCDIF_PIXEL */ 198*4882a593Smuzhiyun #define IMX8MQ_CLK_LCDIF_PIXEL 128 199*4882a593Smuzhiyun /* SAI1~6 */ 200*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI1 129 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI2 130 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI3 131 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI4 132 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI5 133 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI6 134 211*4882a593Smuzhiyun /* SPDIF1 */ 212*4882a593Smuzhiyun #define IMX8MQ_CLK_SPDIF1 135 213*4882a593Smuzhiyun /* SPDIF2 */ 214*4882a593Smuzhiyun #define IMX8MQ_CLK_SPDIF2 136 215*4882a593Smuzhiyun /* ENET_REF */ 216*4882a593Smuzhiyun #define IMX8MQ_CLK_ENET_REF 137 217*4882a593Smuzhiyun /* ENET_TIMER */ 218*4882a593Smuzhiyun #define IMX8MQ_CLK_ENET_TIMER 138 219*4882a593Smuzhiyun /* ENET_PHY */ 220*4882a593Smuzhiyun #define IMX8MQ_CLK_ENET_PHY_REF 139 221*4882a593Smuzhiyun /* NAND */ 222*4882a593Smuzhiyun #define IMX8MQ_CLK_NAND 140 223*4882a593Smuzhiyun /* QSPI */ 224*4882a593Smuzhiyun #define IMX8MQ_CLK_QSPI 141 225*4882a593Smuzhiyun /* USDHC1 */ 226*4882a593Smuzhiyun #define IMX8MQ_CLK_USDHC1 142 227*4882a593Smuzhiyun /* USDHC2 */ 228*4882a593Smuzhiyun #define IMX8MQ_CLK_USDHC2 143 229*4882a593Smuzhiyun /* I2C1 */ 230*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C1 144 231*4882a593Smuzhiyun /* I2C2 */ 232*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C2 145 233*4882a593Smuzhiyun /* I2C3 */ 234*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C3 146 235*4882a593Smuzhiyun /* I2C4 */ 236*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C4 147 237*4882a593Smuzhiyun /* UART1 */ 238*4882a593Smuzhiyun #define IMX8MQ_CLK_UART1 148 239*4882a593Smuzhiyun /* UART2 */ 240*4882a593Smuzhiyun #define IMX8MQ_CLK_UART2 149 241*4882a593Smuzhiyun /* UART3 */ 242*4882a593Smuzhiyun #define IMX8MQ_CLK_UART3 150 243*4882a593Smuzhiyun /* UART4 */ 244*4882a593Smuzhiyun #define IMX8MQ_CLK_UART4 151 245*4882a593Smuzhiyun /* USB_CORE_REF */ 246*4882a593Smuzhiyun #define IMX8MQ_CLK_USB_CORE_REF 152 247*4882a593Smuzhiyun /* USB_PHY_REF */ 248*4882a593Smuzhiyun #define IMX8MQ_CLK_USB_PHY_REF 153 249*4882a593Smuzhiyun /* ECSPI1 */ 250*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI1 154 251*4882a593Smuzhiyun /* ECSPI2 */ 252*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI2 155 253*4882a593Smuzhiyun /* PWM1 */ 254*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM1 156 255*4882a593Smuzhiyun /* PWM2 */ 256*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM2 157 257*4882a593Smuzhiyun /* PWM3 */ 258*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM3 158 259*4882a593Smuzhiyun /* PWM4 */ 260*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM4 159 261*4882a593Smuzhiyun /* GPT1 */ 262*4882a593Smuzhiyun #define IMX8MQ_CLK_GPT1 160 263*4882a593Smuzhiyun /* WDOG */ 264*4882a593Smuzhiyun #define IMX8MQ_CLK_WDOG 161 265*4882a593Smuzhiyun /* WRCLK */ 266*4882a593Smuzhiyun #define IMX8MQ_CLK_WRCLK 162 267*4882a593Smuzhiyun /* DSI_CORE */ 268*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_CORE 163 269*4882a593Smuzhiyun /* DSI_PHY */ 270*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_PHY_REF 164 271*4882a593Smuzhiyun /* DSI_DBI */ 272*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_DBI 165 273*4882a593Smuzhiyun /*DSI_ESC */ 274*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_ESC 166 275*4882a593Smuzhiyun /* CSI1_CORE */ 276*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI1_CORE 167 277*4882a593Smuzhiyun /* CSI1_PHY */ 278*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI1_PHY_REF 168 279*4882a593Smuzhiyun /* CSI_ESC */ 280*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI1_ESC 169 281*4882a593Smuzhiyun /* CSI2_CORE */ 282*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI2_CORE 170 283*4882a593Smuzhiyun /* CSI2_PHY */ 284*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI2_PHY_REF 171 285*4882a593Smuzhiyun /* CSI2_ESC */ 286*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI2_ESC 172 287*4882a593Smuzhiyun /* PCIE2_CTRL */ 288*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE2_CTRL 173 289*4882a593Smuzhiyun /* PCIE2_PHY */ 290*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE2_PHY 174 291*4882a593Smuzhiyun /* PCIE2_AUX */ 292*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE2_AUX 175 293*4882a593Smuzhiyun /* ECSPI3 */ 294*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI3 176 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* CCGR clocks */ 297*4882a593Smuzhiyun #define IMX8MQ_CLK_A53_ROOT 177 298*4882a593Smuzhiyun #define IMX8MQ_CLK_DRAM_ROOT 178 299*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI1_ROOT 179 300*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI2_ROOT 180 301*4882a593Smuzhiyun #define IMX8MQ_CLK_ECSPI3_ROOT 181 302*4882a593Smuzhiyun #define IMX8MQ_CLK_ENET1_ROOT 182 303*4882a593Smuzhiyun #define IMX8MQ_CLK_GPT1_ROOT 183 304*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C1_ROOT 184 305*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C2_ROOT 185 306*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C3_ROOT 186 307*4882a593Smuzhiyun #define IMX8MQ_CLK_I2C4_ROOT 187 308*4882a593Smuzhiyun #define IMX8MQ_CLK_M4_ROOT 188 309*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE1_ROOT 189 310*4882a593Smuzhiyun #define IMX8MQ_CLK_PCIE2_ROOT 190 311*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM1_ROOT 191 312*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM2_ROOT 192 313*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM3_ROOT 193 314*4882a593Smuzhiyun #define IMX8MQ_CLK_PWM4_ROOT 194 315*4882a593Smuzhiyun #define IMX8MQ_CLK_QSPI_ROOT 195 316*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI1_ROOT 196 317*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI2_ROOT 197 318*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI3_ROOT 198 319*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI4_ROOT 199 320*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI5_ROOT 200 321*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI6_ROOT 201 322*4882a593Smuzhiyun #define IMX8MQ_CLK_UART1_ROOT 202 323*4882a593Smuzhiyun #define IMX8MQ_CLK_UART2_ROOT 203 324*4882a593Smuzhiyun #define IMX8MQ_CLK_UART3_ROOT 204 325*4882a593Smuzhiyun #define IMX8MQ_CLK_UART4_ROOT 205 326*4882a593Smuzhiyun #define IMX8MQ_CLK_USB1_CTRL_ROOT 206 327*4882a593Smuzhiyun #define IMX8MQ_CLK_USB2_CTRL_ROOT 207 328*4882a593Smuzhiyun #define IMX8MQ_CLK_USB1_PHY_ROOT 208 329*4882a593Smuzhiyun #define IMX8MQ_CLK_USB2_PHY_ROOT 209 330*4882a593Smuzhiyun #define IMX8MQ_CLK_USDHC1_ROOT 210 331*4882a593Smuzhiyun #define IMX8MQ_CLK_USDHC2_ROOT 211 332*4882a593Smuzhiyun #define IMX8MQ_CLK_WDOG1_ROOT 212 333*4882a593Smuzhiyun #define IMX8MQ_CLK_WDOG2_ROOT 213 334*4882a593Smuzhiyun #define IMX8MQ_CLK_WDOG3_ROOT 214 335*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_ROOT 215 336*4882a593Smuzhiyun #define IMX8MQ_CLK_HEVC_ROOT 216 337*4882a593Smuzhiyun #define IMX8MQ_CLK_AVC_ROOT 217 338*4882a593Smuzhiyun #define IMX8MQ_CLK_VP9_ROOT 218 339*4882a593Smuzhiyun #define IMX8MQ_CLK_HEVC_INTER_ROOT 219 340*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_ROOT 220 341*4882a593Smuzhiyun #define IMX8MQ_CLK_HDMI_ROOT 221 342*4882a593Smuzhiyun #define IMX8MQ_CLK_HDMI_PHY_ROOT 222 343*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_DEC_ROOT 223 344*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI1_ROOT 224 345*4882a593Smuzhiyun #define IMX8MQ_CLK_CSI2_ROOT 225 346*4882a593Smuzhiyun #define IMX8MQ_CLK_RAWNAND_ROOT 226 347*4882a593Smuzhiyun #define IMX8MQ_CLK_SDMA1_ROOT 227 348*4882a593Smuzhiyun #define IMX8MQ_CLK_SDMA2_ROOT 228 349*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_G1_ROOT 229 350*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_G2_ROOT 230 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* SCCG PLL GATE */ 353*4882a593Smuzhiyun #define IMX8MQ_SYS1_PLL_OUT 231 354*4882a593Smuzhiyun #define IMX8MQ_SYS2_PLL_OUT 232 355*4882a593Smuzhiyun #define IMX8MQ_SYS3_PLL_OUT 233 356*4882a593Smuzhiyun #define IMX8MQ_DRAM_PLL_OUT 234 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun #define IMX8MQ_GPT_3M_CLK 235 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun #define IMX8MQ_CLK_IPG_ROOT 236 361*4882a593Smuzhiyun #define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 362*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI1_IPG 238 363*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI2_IPG 239 364*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI3_IPG 240 365*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI4_IPG 241 366*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI5_IPG 242 367*4882a593Smuzhiyun #define IMX8MQ_CLK_SAI6_IPG 243 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* DSI AHB/IPG clocks */ 370*4882a593Smuzhiyun /* rxesc clock */ 371*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_AHB 244 372*4882a593Smuzhiyun /* txesc clock */ 373*4882a593Smuzhiyun #define IMX8MQ_CLK_DSI_IPG_DIV 245 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun #define IMX8MQ_CLK_TMU_ROOT 246 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun /* Display root clocks */ 378*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_AXI_ROOT 247 379*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_APB_ROOT 248 380*4882a593Smuzhiyun #define IMX8MQ_CLK_DISP_RTRM_ROOT 249 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #define IMX8MQ_CLK_OCOTP_ROOT 250 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #define IMX8MQ_CLK_DRAM_ALT_ROOT 251 385*4882a593Smuzhiyun #define IMX8MQ_CLK_DRAM_CORE 252 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun #define IMX8MQ_CLK_MU_ROOT 253 388*4882a593Smuzhiyun #define IMX8MQ_VIDEO2_PLL_OUT 254 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun #define IMX8MQ_CLK_CLKO2 255 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun #define IMX8MQ_CLK_CLKO1 257 395*4882a593Smuzhiyun #define IMX8MQ_CLK_ARM 258 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun #define IMX8MQ_CLK_GPIO1_ROOT 259 398*4882a593Smuzhiyun #define IMX8MQ_CLK_GPIO2_ROOT 260 399*4882a593Smuzhiyun #define IMX8MQ_CLK_GPIO3_ROOT 261 400*4882a593Smuzhiyun #define IMX8MQ_CLK_GPIO4_ROOT 262 401*4882a593Smuzhiyun #define IMX8MQ_CLK_GPIO5_ROOT 263 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #define IMX8MQ_CLK_SNVS_ROOT 264 404*4882a593Smuzhiyun #define IMX8MQ_CLK_GIC 265 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun #define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_CORE 285 409*4882a593Smuzhiyun #define IMX8MQ_CLK_GPU_SHADER 286 410*4882a593Smuzhiyun #define IMX8MQ_CLK_M4_CORE 287 411*4882a593Smuzhiyun #define IMX8MQ_CLK_VPU_CORE 288 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define IMX8MQ_CLK_A53_CORE 289 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define IMX8MQ_CLK_END 290 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ 418