1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2019 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX8MP_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX8MP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX8MP_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX8MP_CLK_32K 1 11*4882a593Smuzhiyun #define IMX8MP_CLK_24M 2 12*4882a593Smuzhiyun #define IMX8MP_OSC_HDMI_CLK 3 13*4882a593Smuzhiyun #define IMX8MP_CLK_EXT1 4 14*4882a593Smuzhiyun #define IMX8MP_CLK_EXT2 5 15*4882a593Smuzhiyun #define IMX8MP_CLK_EXT3 6 16*4882a593Smuzhiyun #define IMX8MP_CLK_EXT4 7 17*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL1_REF_SEL 8 18*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL2_REF_SEL 9 19*4882a593Smuzhiyun #define IMX8MP_VIDEO_PLL1_REF_SEL 10 20*4882a593Smuzhiyun #define IMX8MP_DRAM_PLL_REF_SEL 11 21*4882a593Smuzhiyun #define IMX8MP_GPU_PLL_REF_SEL 12 22*4882a593Smuzhiyun #define IMX8MP_VPU_PLL_REF_SEL 13 23*4882a593Smuzhiyun #define IMX8MP_ARM_PLL_REF_SEL 14 24*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_REF_SEL 15 25*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_REF_SEL 16 26*4882a593Smuzhiyun #define IMX8MP_SYS_PLL3_REF_SEL 17 27*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL1 18 28*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL2 19 29*4882a593Smuzhiyun #define IMX8MP_VIDEO_PLL1 20 30*4882a593Smuzhiyun #define IMX8MP_DRAM_PLL 21 31*4882a593Smuzhiyun #define IMX8MP_GPU_PLL 22 32*4882a593Smuzhiyun #define IMX8MP_VPU_PLL 23 33*4882a593Smuzhiyun #define IMX8MP_ARM_PLL 24 34*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1 25 35*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2 26 36*4882a593Smuzhiyun #define IMX8MP_SYS_PLL3 27 37*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL1_BYPASS 28 38*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL2_BYPASS 29 39*4882a593Smuzhiyun #define IMX8MP_VIDEO_PLL1_BYPASS 30 40*4882a593Smuzhiyun #define IMX8MP_DRAM_PLL_BYPASS 31 41*4882a593Smuzhiyun #define IMX8MP_GPU_PLL_BYPASS 32 42*4882a593Smuzhiyun #define IMX8MP_VPU_PLL_BYPASS 33 43*4882a593Smuzhiyun #define IMX8MP_ARM_PLL_BYPASS 34 44*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_BYPASS 35 45*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_BYPASS 36 46*4882a593Smuzhiyun #define IMX8MP_SYS_PLL3_BYPASS 37 47*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL1_OUT 38 48*4882a593Smuzhiyun #define IMX8MP_AUDIO_PLL2_OUT 39 49*4882a593Smuzhiyun #define IMX8MP_VIDEO_PLL1_OUT 40 50*4882a593Smuzhiyun #define IMX8MP_DRAM_PLL_OUT 41 51*4882a593Smuzhiyun #define IMX8MP_GPU_PLL_OUT 42 52*4882a593Smuzhiyun #define IMX8MP_VPU_PLL_OUT 43 53*4882a593Smuzhiyun #define IMX8MP_ARM_PLL_OUT 44 54*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_OUT 45 55*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_OUT 46 56*4882a593Smuzhiyun #define IMX8MP_SYS_PLL3_OUT 47 57*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_40M 48 58*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_80M 49 59*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_100M 50 60*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_133M 51 61*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_160M 52 62*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_200M 53 63*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_266M 54 64*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_400M 55 65*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_800M 56 66*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_50M 57 67*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_100M 58 68*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_125M 59 69*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_166M 60 70*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_200M 61 71*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_250M 62 72*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_333M 63 73*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_500M 64 74*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_1000M 65 75*4882a593Smuzhiyun #define IMX8MP_CLK_A53_SRC 66 76*4882a593Smuzhiyun #define IMX8MP_CLK_M7_SRC 67 77*4882a593Smuzhiyun #define IMX8MP_CLK_ML_SRC 68 78*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_CORE_SRC 69 79*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_SHADER_SRC 70 80*4882a593Smuzhiyun #define IMX8MP_CLK_GPU2D_SRC 71 81*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_AXI_SRC 72 82*4882a593Smuzhiyun #define IMX8MP_CLK_HSIO_AXI_SRC 73 83*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_ISP_SRC 74 84*4882a593Smuzhiyun #define IMX8MP_CLK_A53_CG 75 85*4882a593Smuzhiyun #define IMX8MP_CLK_M4_CG 76 86*4882a593Smuzhiyun #define IMX8MP_CLK_ML_CG 77 87*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_CORE_CG 78 88*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_SHADER_CG 79 89*4882a593Smuzhiyun #define IMX8MP_CLK_GPU2D_CG 80 90*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_AXI_CG 81 91*4882a593Smuzhiyun #define IMX8MP_CLK_HSIO_AXI_CG 82 92*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_ISP_CG 83 93*4882a593Smuzhiyun #define IMX8MP_CLK_A53_DIV 84 94*4882a593Smuzhiyun #define IMX8MP_CLK_M7_DIV 85 95*4882a593Smuzhiyun #define IMX8MP_CLK_ML_DIV 86 96*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_CORE_DIV 87 97*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_SHADER_DIV 88 98*4882a593Smuzhiyun #define IMX8MP_CLK_GPU2D_DIV 89 99*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_AXI_DIV 90 100*4882a593Smuzhiyun #define IMX8MP_CLK_HSIO_AXI_DIV 91 101*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_ISP_DIV 92 102*4882a593Smuzhiyun #define IMX8MP_CLK_MAIN_AXI 93 103*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_AXI 94 104*4882a593Smuzhiyun #define IMX8MP_CLK_NAND_USDHC_BUS 95 105*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_BUS 96 106*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_AXI 97 107*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_APB 98 108*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_APB 99 109*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_AXI 100 110*4882a593Smuzhiyun #define IMX8MP_CLK_GPU_AXI 101 111*4882a593Smuzhiyun #define IMX8MP_CLK_GPU_AHB 102 112*4882a593Smuzhiyun #define IMX8MP_CLK_NOC 103 113*4882a593Smuzhiyun #define IMX8MP_CLK_NOC_IO 104 114*4882a593Smuzhiyun #define IMX8MP_CLK_ML_AXI 105 115*4882a593Smuzhiyun #define IMX8MP_CLK_ML_AHB 106 116*4882a593Smuzhiyun #define IMX8MP_CLK_AHB 107 117*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_AHB 108 118*4882a593Smuzhiyun #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 119*4882a593Smuzhiyun #define IMX8MP_CLK_IPG_ROOT 110 120*4882a593Smuzhiyun #define IMX8MP_CLK_IPG_AUDIO_ROOT 111 121*4882a593Smuzhiyun #define IMX8MP_CLK_DRAM_ALT 112 122*4882a593Smuzhiyun #define IMX8MP_CLK_DRAM_APB 113 123*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_G1 114 124*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_G2 115 125*4882a593Smuzhiyun #define IMX8MP_CLK_CAN1 116 126*4882a593Smuzhiyun #define IMX8MP_CLK_CAN2 117 127*4882a593Smuzhiyun #define IMX8MP_CLK_MEMREPAIR 118 128*4882a593Smuzhiyun #define IMX8MP_CLK_PCIE_PHY 119 129*4882a593Smuzhiyun #define IMX8MP_CLK_PCIE_AUX 120 130*4882a593Smuzhiyun #define IMX8MP_CLK_I2C5 121 131*4882a593Smuzhiyun #define IMX8MP_CLK_I2C6 122 132*4882a593Smuzhiyun #define IMX8MP_CLK_SAI1 123 133*4882a593Smuzhiyun #define IMX8MP_CLK_SAI2 124 134*4882a593Smuzhiyun #define IMX8MP_CLK_SAI3 125 135*4882a593Smuzhiyun #define IMX8MP_CLK_SAI4 126 136*4882a593Smuzhiyun #define IMX8MP_CLK_SAI5 127 137*4882a593Smuzhiyun #define IMX8MP_CLK_SAI6 128 138*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_QOS 129 139*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_QOS_TIMER 130 140*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_REF 131 141*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_TIMER 132 142*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_PHY_REF 133 143*4882a593Smuzhiyun #define IMX8MP_CLK_NAND 134 144*4882a593Smuzhiyun #define IMX8MP_CLK_QSPI 135 145*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC1 136 146*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC2 137 147*4882a593Smuzhiyun #define IMX8MP_CLK_I2C1 138 148*4882a593Smuzhiyun #define IMX8MP_CLK_I2C2 139 149*4882a593Smuzhiyun #define IMX8MP_CLK_I2C3 140 150*4882a593Smuzhiyun #define IMX8MP_CLK_I2C4 141 151*4882a593Smuzhiyun #define IMX8MP_CLK_UART1 142 152*4882a593Smuzhiyun #define IMX8MP_CLK_UART2 143 153*4882a593Smuzhiyun #define IMX8MP_CLK_UART3 144 154*4882a593Smuzhiyun #define IMX8MP_CLK_UART4 145 155*4882a593Smuzhiyun #define IMX8MP_CLK_USB_CORE_REF 146 156*4882a593Smuzhiyun #define IMX8MP_CLK_USB_PHY_REF 147 157*4882a593Smuzhiyun #define IMX8MP_CLK_GIC 148 158*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI1 149 159*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI2 150 160*4882a593Smuzhiyun #define IMX8MP_CLK_PWM1 151 161*4882a593Smuzhiyun #define IMX8MP_CLK_PWM2 152 162*4882a593Smuzhiyun #define IMX8MP_CLK_PWM3 153 163*4882a593Smuzhiyun #define IMX8MP_CLK_PWM4 154 164*4882a593Smuzhiyun #define IMX8MP_CLK_GPT1 155 165*4882a593Smuzhiyun #define IMX8MP_CLK_GPT2 156 166*4882a593Smuzhiyun #define IMX8MP_CLK_GPT3 157 167*4882a593Smuzhiyun #define IMX8MP_CLK_GPT4 158 168*4882a593Smuzhiyun #define IMX8MP_CLK_GPT5 159 169*4882a593Smuzhiyun #define IMX8MP_CLK_GPT6 160 170*4882a593Smuzhiyun #define IMX8MP_CLK_TRACE 161 171*4882a593Smuzhiyun #define IMX8MP_CLK_WDOG 162 172*4882a593Smuzhiyun #define IMX8MP_CLK_WRCLK 163 173*4882a593Smuzhiyun #define IMX8MP_CLK_IPP_DO_CLKO1 164 174*4882a593Smuzhiyun #define IMX8MP_CLK_IPP_DO_CLKO2 165 175*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_FDCC_TST 166 176*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_24M 167 177*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_REF_266M 168 178*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC3 169 179*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_CAM1_PIX 170 180*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 181*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_DISP1_PIX 172 182*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_CAM2_PIX 173 183*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_LDB 174 184*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 185*4882a593Smuzhiyun #define IMX8MP_CLK_PCIE2_CTRL 176 186*4882a593Smuzhiyun #define IMX8MP_CLK_PCIE2_PHY 177 187*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 188*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI3 179 189*4882a593Smuzhiyun #define IMX8MP_CLK_PDM 180 190*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_VC8000E 181 191*4882a593Smuzhiyun #define IMX8MP_CLK_SAI7 182 192*4882a593Smuzhiyun #define IMX8MP_CLK_GPC_ROOT 183 193*4882a593Smuzhiyun #define IMX8MP_CLK_ANAMIX_ROOT 184 194*4882a593Smuzhiyun #define IMX8MP_CLK_CPU_ROOT 185 195*4882a593Smuzhiyun #define IMX8MP_CLK_CSU_ROOT 186 196*4882a593Smuzhiyun #define IMX8MP_CLK_DEBUG_ROOT 187 197*4882a593Smuzhiyun #define IMX8MP_CLK_DRAM1_ROOT 188 198*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI1_ROOT 189 199*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI2_ROOT 190 200*4882a593Smuzhiyun #define IMX8MP_CLK_ECSPI3_ROOT 191 201*4882a593Smuzhiyun #define IMX8MP_CLK_ENET1_ROOT 192 202*4882a593Smuzhiyun #define IMX8MP_CLK_GPIO1_ROOT 193 203*4882a593Smuzhiyun #define IMX8MP_CLK_GPIO2_ROOT 194 204*4882a593Smuzhiyun #define IMX8MP_CLK_GPIO3_ROOT 195 205*4882a593Smuzhiyun #define IMX8MP_CLK_GPIO4_ROOT 196 206*4882a593Smuzhiyun #define IMX8MP_CLK_GPIO5_ROOT 197 207*4882a593Smuzhiyun #define IMX8MP_CLK_GPT1_ROOT 198 208*4882a593Smuzhiyun #define IMX8MP_CLK_GPT2_ROOT 199 209*4882a593Smuzhiyun #define IMX8MP_CLK_GPT3_ROOT 200 210*4882a593Smuzhiyun #define IMX8MP_CLK_GPT4_ROOT 201 211*4882a593Smuzhiyun #define IMX8MP_CLK_GPT5_ROOT 202 212*4882a593Smuzhiyun #define IMX8MP_CLK_GPT6_ROOT 203 213*4882a593Smuzhiyun #define IMX8MP_CLK_HS_ROOT 204 214*4882a593Smuzhiyun #define IMX8MP_CLK_I2C1_ROOT 205 215*4882a593Smuzhiyun #define IMX8MP_CLK_I2C2_ROOT 206 216*4882a593Smuzhiyun #define IMX8MP_CLK_I2C3_ROOT 207 217*4882a593Smuzhiyun #define IMX8MP_CLK_I2C4_ROOT 208 218*4882a593Smuzhiyun #define IMX8MP_CLK_IOMUX_ROOT 209 219*4882a593Smuzhiyun #define IMX8MP_CLK_IPMUX1_ROOT 210 220*4882a593Smuzhiyun #define IMX8MP_CLK_IPMUX2_ROOT 211 221*4882a593Smuzhiyun #define IMX8MP_CLK_IPMUX3_ROOT 212 222*4882a593Smuzhiyun #define IMX8MP_CLK_MU_ROOT 213 223*4882a593Smuzhiyun #define IMX8MP_CLK_OCOTP_ROOT 214 224*4882a593Smuzhiyun #define IMX8MP_CLK_OCRAM_ROOT 215 225*4882a593Smuzhiyun #define IMX8MP_CLK_OCRAM_S_ROOT 216 226*4882a593Smuzhiyun #define IMX8MP_CLK_PCIE_ROOT 217 227*4882a593Smuzhiyun #define IMX8MP_CLK_PERFMON1_ROOT 218 228*4882a593Smuzhiyun #define IMX8MP_CLK_PERFMON2_ROOT 219 229*4882a593Smuzhiyun #define IMX8MP_CLK_PWM1_ROOT 220 230*4882a593Smuzhiyun #define IMX8MP_CLK_PWM2_ROOT 221 231*4882a593Smuzhiyun #define IMX8MP_CLK_PWM3_ROOT 222 232*4882a593Smuzhiyun #define IMX8MP_CLK_PWM4_ROOT 223 233*4882a593Smuzhiyun #define IMX8MP_CLK_QOS_ROOT 224 234*4882a593Smuzhiyun #define IMX8MP_CLK_QOS_ENET_ROOT 225 235*4882a593Smuzhiyun #define IMX8MP_CLK_QSPI_ROOT 226 236*4882a593Smuzhiyun #define IMX8MP_CLK_NAND_ROOT 227 237*4882a593Smuzhiyun #define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 238*4882a593Smuzhiyun #define IMX8MP_CLK_RDC_ROOT 229 239*4882a593Smuzhiyun #define IMX8MP_CLK_ROM_ROOT 230 240*4882a593Smuzhiyun #define IMX8MP_CLK_I2C5_ROOT 231 241*4882a593Smuzhiyun #define IMX8MP_CLK_I2C6_ROOT 232 242*4882a593Smuzhiyun #define IMX8MP_CLK_CAN1_ROOT 233 243*4882a593Smuzhiyun #define IMX8MP_CLK_CAN2_ROOT 234 244*4882a593Smuzhiyun #define IMX8MP_CLK_SCTR_ROOT 235 245*4882a593Smuzhiyun #define IMX8MP_CLK_SDMA1_ROOT 236 246*4882a593Smuzhiyun #define IMX8MP_CLK_ENET_QOS_ROOT 237 247*4882a593Smuzhiyun #define IMX8MP_CLK_SEC_DEBUG_ROOT 238 248*4882a593Smuzhiyun #define IMX8MP_CLK_SEMA1_ROOT 239 249*4882a593Smuzhiyun #define IMX8MP_CLK_SEMA2_ROOT 240 250*4882a593Smuzhiyun #define IMX8MP_CLK_IRQ_STEER_ROOT 241 251*4882a593Smuzhiyun #define IMX8MP_CLK_SIM_ENET_ROOT 242 252*4882a593Smuzhiyun #define IMX8MP_CLK_SIM_M_ROOT 243 253*4882a593Smuzhiyun #define IMX8MP_CLK_SIM_MAIN_ROOT 244 254*4882a593Smuzhiyun #define IMX8MP_CLK_SIM_S_ROOT 245 255*4882a593Smuzhiyun #define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 256*4882a593Smuzhiyun #define IMX8MP_CLK_GPU2D_ROOT 247 257*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_ROOT 248 258*4882a593Smuzhiyun #define IMX8MP_CLK_SNVS_ROOT 249 259*4882a593Smuzhiyun #define IMX8MP_CLK_TRACE_ROOT 250 260*4882a593Smuzhiyun #define IMX8MP_CLK_UART1_ROOT 251 261*4882a593Smuzhiyun #define IMX8MP_CLK_UART2_ROOT 252 262*4882a593Smuzhiyun #define IMX8MP_CLK_UART3_ROOT 253 263*4882a593Smuzhiyun #define IMX8MP_CLK_UART4_ROOT 254 264*4882a593Smuzhiyun #define IMX8MP_CLK_USB_ROOT 255 265*4882a593Smuzhiyun #define IMX8MP_CLK_USB_PHY_ROOT 256 266*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC1_ROOT 257 267*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC2_ROOT 258 268*4882a593Smuzhiyun #define IMX8MP_CLK_WDOG1_ROOT 259 269*4882a593Smuzhiyun #define IMX8MP_CLK_WDOG2_ROOT 260 270*4882a593Smuzhiyun #define IMX8MP_CLK_WDOG3_ROOT 261 271*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_G1_ROOT 262 272*4882a593Smuzhiyun #define IMX8MP_CLK_GPU_ROOT 263 273*4882a593Smuzhiyun #define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 274*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_VC8KE_ROOT 265 275*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_G2_ROOT 266 276*4882a593Smuzhiyun #define IMX8MP_CLK_NPU_ROOT 267 277*4882a593Smuzhiyun #define IMX8MP_CLK_HSIO_ROOT 268 278*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_APB_ROOT 269 279*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_AXI_ROOT 270 280*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 281*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 282*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 283*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 284*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 285*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_ISP_ROOT 276 286*4882a593Smuzhiyun #define IMX8MP_CLK_USDHC3_ROOT 277 287*4882a593Smuzhiyun #define IMX8MP_CLK_HDMI_ROOT 278 288*4882a593Smuzhiyun #define IMX8MP_CLK_XTAL_ROOT 279 289*4882a593Smuzhiyun #define IMX8MP_CLK_PLL_ROOT 280 290*4882a593Smuzhiyun #define IMX8MP_CLK_TSENSOR_ROOT 281 291*4882a593Smuzhiyun #define IMX8MP_CLK_VPU_ROOT 282 292*4882a593Smuzhiyun #define IMX8MP_CLK_MRPR_ROOT 283 293*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_ROOT 284 294*4882a593Smuzhiyun #define IMX8MP_CLK_DRAM_ALT_ROOT 285 295*4882a593Smuzhiyun #define IMX8MP_CLK_DRAM_CORE 286 296*4882a593Smuzhiyun #define IMX8MP_CLK_ARM 287 297*4882a593Smuzhiyun #define IMX8MP_CLK_A53_CORE 288 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_40M_CG 289 300*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_80M_CG 290 301*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_100M_CG 291 302*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_133M_CG 292 303*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_160M_CG 293 304*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_200M_CG 294 305*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_266M_CG 295 306*4882a593Smuzhiyun #define IMX8MP_SYS_PLL1_400M_CG 296 307*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_50M_CG 297 308*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_100M_CG 298 309*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_125M_CG 299 310*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_166M_CG 300 311*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_200M_CG 301 312*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_250M_CG 302 313*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_333M_CG 303 314*4882a593Smuzhiyun #define IMX8MP_SYS_PLL2_500M_CG 304 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun #define IMX8MP_CLK_M7_CORE 305 317*4882a593Smuzhiyun #define IMX8MP_CLK_ML_CORE 306 318*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_CORE 307 319*4882a593Smuzhiyun #define IMX8MP_CLK_GPU3D_SHADER_CORE 308 320*4882a593Smuzhiyun #define IMX8MP_CLK_GPU2D_CORE 309 321*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIO_AXI 310 322*4882a593Smuzhiyun #define IMX8MP_CLK_HSIO_AXI 311 323*4882a593Smuzhiyun #define IMX8MP_CLK_MEDIA_ISP 312 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define IMX8MP_CLK_END 313 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 328*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 329*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 330*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 331*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 332*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 333*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 334*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 335*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 336*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 337*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 338*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 339*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 340*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 341*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 342*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 343*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 344*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 345*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 346*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 347*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 348*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 349*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 350*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 351*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 352*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 353*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 354*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 355*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 356*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 357*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 358*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 359*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 360*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 361*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 362*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 363*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 364*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 365*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 366*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 367*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 368*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 369*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 370*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 371*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 372*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 373*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 374*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 375*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 376*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 377*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 378*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 379*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 380*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 381*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 382*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 383*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 384*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 385*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun #define IMX8MP_CLK_AUDIOMIX_END 59 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun #endif 390