1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018-2019 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX8MN_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX8MN_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX8MN_CLK_32K 1 11*4882a593Smuzhiyun #define IMX8MN_CLK_24M 2 12*4882a593Smuzhiyun #define IMX8MN_OSC_HDMI_CLK 3 13*4882a593Smuzhiyun #define IMX8MN_CLK_EXT1 4 14*4882a593Smuzhiyun #define IMX8MN_CLK_EXT2 5 15*4882a593Smuzhiyun #define IMX8MN_CLK_EXT3 6 16*4882a593Smuzhiyun #define IMX8MN_CLK_EXT4 7 17*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL1_REF_SEL 8 18*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL2_REF_SEL 9 19*4882a593Smuzhiyun #define IMX8MN_VIDEO_PLL1_REF_SEL 10 20*4882a593Smuzhiyun #define IMX8MN_DRAM_PLL_REF_SEL 11 21*4882a593Smuzhiyun #define IMX8MN_GPU_PLL_REF_SEL 12 22*4882a593Smuzhiyun #define IMX8MN_VPU_PLL_REF_SEL 13 23*4882a593Smuzhiyun #define IMX8MN_ARM_PLL_REF_SEL 14 24*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_REF_SEL 15 25*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_REF_SEL 16 26*4882a593Smuzhiyun #define IMX8MN_SYS_PLL3_REF_SEL 17 27*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL1 18 28*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL2 19 29*4882a593Smuzhiyun #define IMX8MN_VIDEO_PLL1 20 30*4882a593Smuzhiyun #define IMX8MN_DRAM_PLL 21 31*4882a593Smuzhiyun #define IMX8MN_GPU_PLL 22 32*4882a593Smuzhiyun #define IMX8MN_VPU_PLL 23 33*4882a593Smuzhiyun #define IMX8MN_ARM_PLL 24 34*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1 25 35*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2 26 36*4882a593Smuzhiyun #define IMX8MN_SYS_PLL3 27 37*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL1_BYPASS 28 38*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL2_BYPASS 29 39*4882a593Smuzhiyun #define IMX8MN_VIDEO_PLL1_BYPASS 30 40*4882a593Smuzhiyun #define IMX8MN_DRAM_PLL_BYPASS 31 41*4882a593Smuzhiyun #define IMX8MN_GPU_PLL_BYPASS 32 42*4882a593Smuzhiyun #define IMX8MN_VPU_PLL_BYPASS 33 43*4882a593Smuzhiyun #define IMX8MN_ARM_PLL_BYPASS 34 44*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_BYPASS 35 45*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_BYPASS 36 46*4882a593Smuzhiyun #define IMX8MN_SYS_PLL3_BYPASS 37 47*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL1_OUT 38 48*4882a593Smuzhiyun #define IMX8MN_AUDIO_PLL2_OUT 39 49*4882a593Smuzhiyun #define IMX8MN_VIDEO_PLL1_OUT 40 50*4882a593Smuzhiyun #define IMX8MN_DRAM_PLL_OUT 41 51*4882a593Smuzhiyun #define IMX8MN_GPU_PLL_OUT 42 52*4882a593Smuzhiyun #define IMX8MN_VPU_PLL_OUT 43 53*4882a593Smuzhiyun #define IMX8MN_ARM_PLL_OUT 44 54*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_OUT 45 55*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_OUT 46 56*4882a593Smuzhiyun #define IMX8MN_SYS_PLL3_OUT 47 57*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_40M 48 58*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_80M 49 59*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_100M 50 60*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_133M 51 61*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_160M 52 62*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_200M 53 63*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_266M 54 64*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_400M 55 65*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_800M 56 66*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_50M 57 67*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_100M 58 68*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_125M 59 69*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_166M 60 70*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_200M 61 71*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_250M 62 72*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_333M 63 73*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_500M 64 74*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_1000M 65 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* CORE CLOCK ROOT */ 77*4882a593Smuzhiyun #define IMX8MN_CLK_A53_SRC 66 78*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_CORE_SRC 67 79*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_SHADER_SRC 68 80*4882a593Smuzhiyun #define IMX8MN_CLK_A53_CG 69 81*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_CORE_CG 70 82*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_SHADER_CG 71 83*4882a593Smuzhiyun #define IMX8MN_CLK_A53_DIV 72 84*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_CORE_DIV 73 85*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_SHADER_DIV 74 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* BUS CLOCK ROOT */ 88*4882a593Smuzhiyun #define IMX8MN_CLK_MAIN_AXI 75 89*4882a593Smuzhiyun #define IMX8MN_CLK_ENET_AXI 76 90*4882a593Smuzhiyun #define IMX8MN_CLK_NAND_USDHC_BUS 77 91*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_AXI 78 92*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_APB 79 93*4882a593Smuzhiyun #define IMX8MN_CLK_USB_BUS 80 94*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_AXI 81 95*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_AHB 82 96*4882a593Smuzhiyun #define IMX8MN_CLK_NOC 83 97*4882a593Smuzhiyun #define IMX8MN_CLK_AHB 84 98*4882a593Smuzhiyun #define IMX8MN_CLK_AUDIO_AHB 85 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* IPG CLOCK ROOT */ 101*4882a593Smuzhiyun #define IMX8MN_CLK_IPG_ROOT 86 102*4882a593Smuzhiyun #define IMX8MN_CLK_IPG_AUDIO_ROOT 87 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* IP */ 105*4882a593Smuzhiyun #define IMX8MN_CLK_DRAM_CORE 88 106*4882a593Smuzhiyun #define IMX8MN_CLK_DRAM_ALT 89 107*4882a593Smuzhiyun #define IMX8MN_CLK_DRAM_APB 90 108*4882a593Smuzhiyun #define IMX8MN_CLK_DRAM_ALT_ROOT 91 109*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_PIXEL 92 110*4882a593Smuzhiyun #define IMX8MN_CLK_SAI2 93 111*4882a593Smuzhiyun #define IMX8MN_CLK_SAI3 94 112*4882a593Smuzhiyun #define IMX8MN_CLK_SAI5 95 113*4882a593Smuzhiyun #define IMX8MN_CLK_SAI6 96 114*4882a593Smuzhiyun #define IMX8MN_CLK_SPDIF1 97 115*4882a593Smuzhiyun #define IMX8MN_CLK_ENET_REF 98 116*4882a593Smuzhiyun #define IMX8MN_CLK_ENET_TIMER 99 117*4882a593Smuzhiyun #define IMX8MN_CLK_ENET_PHY_REF 100 118*4882a593Smuzhiyun #define IMX8MN_CLK_NAND 101 119*4882a593Smuzhiyun #define IMX8MN_CLK_QSPI 102 120*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC1 103 121*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC2 104 122*4882a593Smuzhiyun #define IMX8MN_CLK_I2C1 105 123*4882a593Smuzhiyun #define IMX8MN_CLK_I2C2 106 124*4882a593Smuzhiyun #define IMX8MN_CLK_I2C3 107 125*4882a593Smuzhiyun #define IMX8MN_CLK_I2C4 108 126*4882a593Smuzhiyun #define IMX8MN_CLK_UART1 109 127*4882a593Smuzhiyun #define IMX8MN_CLK_UART2 110 128*4882a593Smuzhiyun #define IMX8MN_CLK_UART3 111 129*4882a593Smuzhiyun #define IMX8MN_CLK_UART4 112 130*4882a593Smuzhiyun #define IMX8MN_CLK_USB_CORE_REF 113 131*4882a593Smuzhiyun #define IMX8MN_CLK_USB_PHY_REF 114 132*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI1 115 133*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI2 116 134*4882a593Smuzhiyun #define IMX8MN_CLK_PWM1 117 135*4882a593Smuzhiyun #define IMX8MN_CLK_PWM2 118 136*4882a593Smuzhiyun #define IMX8MN_CLK_PWM3 119 137*4882a593Smuzhiyun #define IMX8MN_CLK_PWM4 120 138*4882a593Smuzhiyun #define IMX8MN_CLK_WDOG 121 139*4882a593Smuzhiyun #define IMX8MN_CLK_WRCLK 122 140*4882a593Smuzhiyun #define IMX8MN_CLK_CLKO1 123 141*4882a593Smuzhiyun #define IMX8MN_CLK_CLKO2 124 142*4882a593Smuzhiyun #define IMX8MN_CLK_DSI_CORE 125 143*4882a593Smuzhiyun #define IMX8MN_CLK_DSI_PHY_REF 126 144*4882a593Smuzhiyun #define IMX8MN_CLK_DSI_DBI 127 145*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC3 128 146*4882a593Smuzhiyun #define IMX8MN_CLK_CAMERA_PIXEL 129 147*4882a593Smuzhiyun #define IMX8MN_CLK_CSI1_PHY_REF 130 148*4882a593Smuzhiyun #define IMX8MN_CLK_CSI2_PHY_REF 131 149*4882a593Smuzhiyun #define IMX8MN_CLK_CSI2_ESC 132 150*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI3 133 151*4882a593Smuzhiyun #define IMX8MN_CLK_PDM 134 152*4882a593Smuzhiyun #define IMX8MN_CLK_SAI7 135 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI1_ROOT 136 155*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI2_ROOT 137 156*4882a593Smuzhiyun #define IMX8MN_CLK_ECSPI3_ROOT 138 157*4882a593Smuzhiyun #define IMX8MN_CLK_ENET1_ROOT 139 158*4882a593Smuzhiyun #define IMX8MN_CLK_GPIO1_ROOT 140 159*4882a593Smuzhiyun #define IMX8MN_CLK_GPIO2_ROOT 141 160*4882a593Smuzhiyun #define IMX8MN_CLK_GPIO3_ROOT 142 161*4882a593Smuzhiyun #define IMX8MN_CLK_GPIO4_ROOT 143 162*4882a593Smuzhiyun #define IMX8MN_CLK_GPIO5_ROOT 144 163*4882a593Smuzhiyun #define IMX8MN_CLK_I2C1_ROOT 145 164*4882a593Smuzhiyun #define IMX8MN_CLK_I2C2_ROOT 146 165*4882a593Smuzhiyun #define IMX8MN_CLK_I2C3_ROOT 147 166*4882a593Smuzhiyun #define IMX8MN_CLK_I2C4_ROOT 148 167*4882a593Smuzhiyun #define IMX8MN_CLK_MU_ROOT 149 168*4882a593Smuzhiyun #define IMX8MN_CLK_OCOTP_ROOT 150 169*4882a593Smuzhiyun #define IMX8MN_CLK_PWM1_ROOT 151 170*4882a593Smuzhiyun #define IMX8MN_CLK_PWM2_ROOT 152 171*4882a593Smuzhiyun #define IMX8MN_CLK_PWM3_ROOT 153 172*4882a593Smuzhiyun #define IMX8MN_CLK_PWM4_ROOT 154 173*4882a593Smuzhiyun #define IMX8MN_CLK_QSPI_ROOT 155 174*4882a593Smuzhiyun #define IMX8MN_CLK_NAND_ROOT 156 175*4882a593Smuzhiyun #define IMX8MN_CLK_SAI2_ROOT 157 176*4882a593Smuzhiyun #define IMX8MN_CLK_SAI2_IPG 158 177*4882a593Smuzhiyun #define IMX8MN_CLK_SAI3_ROOT 159 178*4882a593Smuzhiyun #define IMX8MN_CLK_SAI3_IPG 160 179*4882a593Smuzhiyun #define IMX8MN_CLK_SAI5_ROOT 161 180*4882a593Smuzhiyun #define IMX8MN_CLK_SAI5_IPG 162 181*4882a593Smuzhiyun #define IMX8MN_CLK_SAI6_ROOT 163 182*4882a593Smuzhiyun #define IMX8MN_CLK_SAI6_IPG 164 183*4882a593Smuzhiyun #define IMX8MN_CLK_SAI7_ROOT 165 184*4882a593Smuzhiyun #define IMX8MN_CLK_SAI7_IPG 166 185*4882a593Smuzhiyun #define IMX8MN_CLK_SDMA1_ROOT 167 186*4882a593Smuzhiyun #define IMX8MN_CLK_SDMA2_ROOT 168 187*4882a593Smuzhiyun #define IMX8MN_CLK_UART1_ROOT 169 188*4882a593Smuzhiyun #define IMX8MN_CLK_UART2_ROOT 170 189*4882a593Smuzhiyun #define IMX8MN_CLK_UART3_ROOT 171 190*4882a593Smuzhiyun #define IMX8MN_CLK_UART4_ROOT 172 191*4882a593Smuzhiyun #define IMX8MN_CLK_USB1_CTRL_ROOT 173 192*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC1_ROOT 174 193*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC2_ROOT 175 194*4882a593Smuzhiyun #define IMX8MN_CLK_WDOG1_ROOT 176 195*4882a593Smuzhiyun #define IMX8MN_CLK_WDOG2_ROOT 177 196*4882a593Smuzhiyun #define IMX8MN_CLK_WDOG3_ROOT 178 197*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_BUS_ROOT 179 198*4882a593Smuzhiyun #define IMX8MN_CLK_ASRC_ROOT 180 199*4882a593Smuzhiyun #define IMX8MN_CLK_GPU3D_ROOT 181 200*4882a593Smuzhiyun #define IMX8MN_CLK_PDM_ROOT 182 201*4882a593Smuzhiyun #define IMX8MN_CLK_PDM_IPG 183 202*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_AXI_ROOT 184 203*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_APB_ROOT 185 204*4882a593Smuzhiyun #define IMX8MN_CLK_DISP_PIXEL_ROOT 186 205*4882a593Smuzhiyun #define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 206*4882a593Smuzhiyun #define IMX8MN_CLK_USDHC3_ROOT 188 207*4882a593Smuzhiyun #define IMX8MN_CLK_SDMA3_ROOT 189 208*4882a593Smuzhiyun #define IMX8MN_CLK_TMU_ROOT 190 209*4882a593Smuzhiyun #define IMX8MN_CLK_ARM 191 210*4882a593Smuzhiyun #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 211*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_CORE_ROOT 193 212*4882a593Smuzhiyun #define IMX8MN_CLK_GIC 194 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_40M_CG 195 215*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_80M_CG 196 216*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_100M_CG 197 217*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_133M_CG 198 218*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_160M_CG 199 219*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_200M_CG 200 220*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_266M_CG 201 221*4882a593Smuzhiyun #define IMX8MN_SYS_PLL1_400M_CG 202 222*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_50M_CG 203 223*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_100M_CG 204 224*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_125M_CG 205 225*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_166M_CG 206 226*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_200M_CG 207 227*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_250M_CG 208 228*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_333M_CG 209 229*4882a593Smuzhiyun #define IMX8MN_SYS_PLL2_500M_CG 210 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define IMX8MN_CLK_SNVS_ROOT 211 232*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_CORE 212 233*4882a593Smuzhiyun #define IMX8MN_CLK_GPU_SHADER 213 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define IMX8MN_CLK_A53_CORE 214 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define IMX8MN_CLK_END 215 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #endif 240