1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017-2018 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX8MM_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX8MM_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX8MM_CLK_32K 1 11*4882a593Smuzhiyun #define IMX8MM_CLK_24M 2 12*4882a593Smuzhiyun #define IMX8MM_OSC_HDMI_CLK 3 13*4882a593Smuzhiyun #define IMX8MM_CLK_EXT1 4 14*4882a593Smuzhiyun #define IMX8MM_CLK_EXT2 5 15*4882a593Smuzhiyun #define IMX8MM_CLK_EXT3 6 16*4882a593Smuzhiyun #define IMX8MM_CLK_EXT4 7 17*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL1_REF_SEL 8 18*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL2_REF_SEL 9 19*4882a593Smuzhiyun #define IMX8MM_VIDEO_PLL1_REF_SEL 10 20*4882a593Smuzhiyun #define IMX8MM_DRAM_PLL_REF_SEL 11 21*4882a593Smuzhiyun #define IMX8MM_GPU_PLL_REF_SEL 12 22*4882a593Smuzhiyun #define IMX8MM_VPU_PLL_REF_SEL 13 23*4882a593Smuzhiyun #define IMX8MM_ARM_PLL_REF_SEL 14 24*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_REF_SEL 15 25*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_REF_SEL 16 26*4882a593Smuzhiyun #define IMX8MM_SYS_PLL3_REF_SEL 17 27*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL1 18 28*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL2 19 29*4882a593Smuzhiyun #define IMX8MM_VIDEO_PLL1 20 30*4882a593Smuzhiyun #define IMX8MM_DRAM_PLL 21 31*4882a593Smuzhiyun #define IMX8MM_GPU_PLL 22 32*4882a593Smuzhiyun #define IMX8MM_VPU_PLL 23 33*4882a593Smuzhiyun #define IMX8MM_ARM_PLL 24 34*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1 25 35*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2 26 36*4882a593Smuzhiyun #define IMX8MM_SYS_PLL3 27 37*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL1_BYPASS 28 38*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL2_BYPASS 29 39*4882a593Smuzhiyun #define IMX8MM_VIDEO_PLL1_BYPASS 30 40*4882a593Smuzhiyun #define IMX8MM_DRAM_PLL_BYPASS 31 41*4882a593Smuzhiyun #define IMX8MM_GPU_PLL_BYPASS 32 42*4882a593Smuzhiyun #define IMX8MM_VPU_PLL_BYPASS 33 43*4882a593Smuzhiyun #define IMX8MM_ARM_PLL_BYPASS 34 44*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_BYPASS 35 45*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_BYPASS 36 46*4882a593Smuzhiyun #define IMX8MM_SYS_PLL3_BYPASS 37 47*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL1_OUT 38 48*4882a593Smuzhiyun #define IMX8MM_AUDIO_PLL2_OUT 39 49*4882a593Smuzhiyun #define IMX8MM_VIDEO_PLL1_OUT 40 50*4882a593Smuzhiyun #define IMX8MM_DRAM_PLL_OUT 41 51*4882a593Smuzhiyun #define IMX8MM_GPU_PLL_OUT 42 52*4882a593Smuzhiyun #define IMX8MM_VPU_PLL_OUT 43 53*4882a593Smuzhiyun #define IMX8MM_ARM_PLL_OUT 44 54*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_OUT 45 55*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_OUT 46 56*4882a593Smuzhiyun #define IMX8MM_SYS_PLL3_OUT 47 57*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_40M 48 58*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_80M 49 59*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_100M 50 60*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_133M 51 61*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_160M 52 62*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_200M 53 63*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_266M 54 64*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_400M 55 65*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_800M 56 66*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_50M 57 67*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_100M 58 68*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_125M 59 69*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_166M 60 70*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_200M 61 71*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_250M 62 72*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_333M 63 73*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_500M 64 74*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_1000M 65 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* core */ 77*4882a593Smuzhiyun #define IMX8MM_CLK_A53_SRC 66 78*4882a593Smuzhiyun #define IMX8MM_CLK_M4_SRC 67 79*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_SRC 68 80*4882a593Smuzhiyun #define IMX8MM_CLK_GPU3D_SRC 69 81*4882a593Smuzhiyun #define IMX8MM_CLK_GPU2D_SRC 70 82*4882a593Smuzhiyun #define IMX8MM_CLK_A53_CG 71 83*4882a593Smuzhiyun #define IMX8MM_CLK_M4_CG 72 84*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_CG 73 85*4882a593Smuzhiyun #define IMX8MM_CLK_GPU3D_CG 74 86*4882a593Smuzhiyun #define IMX8MM_CLK_GPU2D_CG 75 87*4882a593Smuzhiyun #define IMX8MM_CLK_A53_DIV 76 88*4882a593Smuzhiyun #define IMX8MM_CLK_M4_DIV 77 89*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_DIV 78 90*4882a593Smuzhiyun #define IMX8MM_CLK_GPU3D_DIV 79 91*4882a593Smuzhiyun #define IMX8MM_CLK_GPU2D_DIV 80 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* bus */ 94*4882a593Smuzhiyun #define IMX8MM_CLK_MAIN_AXI 81 95*4882a593Smuzhiyun #define IMX8MM_CLK_ENET_AXI 82 96*4882a593Smuzhiyun #define IMX8MM_CLK_NAND_USDHC_BUS 83 97*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_BUS 84 98*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_AXI 85 99*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_APB 86 100*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_RTRM 87 101*4882a593Smuzhiyun #define IMX8MM_CLK_USB_BUS 88 102*4882a593Smuzhiyun #define IMX8MM_CLK_GPU_AXI 89 103*4882a593Smuzhiyun #define IMX8MM_CLK_GPU_AHB 90 104*4882a593Smuzhiyun #define IMX8MM_CLK_NOC 91 105*4882a593Smuzhiyun #define IMX8MM_CLK_NOC_APB 92 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define IMX8MM_CLK_AHB 93 108*4882a593Smuzhiyun #define IMX8MM_CLK_AUDIO_AHB 94 109*4882a593Smuzhiyun #define IMX8MM_CLK_IPG_ROOT 95 110*4882a593Smuzhiyun #define IMX8MM_CLK_IPG_AUDIO_ROOT 96 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define IMX8MM_CLK_DRAM_ALT 97 113*4882a593Smuzhiyun #define IMX8MM_CLK_DRAM_APB 98 114*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_G1 99 115*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_G2 100 116*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_DTRC 101 117*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_DC8000 102 118*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE1_CTRL 103 119*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE1_PHY 104 120*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE1_AUX 105 121*4882a593Smuzhiyun #define IMX8MM_CLK_DC_PIXEL 106 122*4882a593Smuzhiyun #define IMX8MM_CLK_LCDIF_PIXEL 107 123*4882a593Smuzhiyun #define IMX8MM_CLK_SAI1 108 124*4882a593Smuzhiyun #define IMX8MM_CLK_SAI2 109 125*4882a593Smuzhiyun #define IMX8MM_CLK_SAI3 110 126*4882a593Smuzhiyun #define IMX8MM_CLK_SAI4 111 127*4882a593Smuzhiyun #define IMX8MM_CLK_SAI5 112 128*4882a593Smuzhiyun #define IMX8MM_CLK_SAI6 113 129*4882a593Smuzhiyun #define IMX8MM_CLK_SPDIF1 114 130*4882a593Smuzhiyun #define IMX8MM_CLK_SPDIF2 115 131*4882a593Smuzhiyun #define IMX8MM_CLK_ENET_REF 116 132*4882a593Smuzhiyun #define IMX8MM_CLK_ENET_TIMER 117 133*4882a593Smuzhiyun #define IMX8MM_CLK_ENET_PHY_REF 118 134*4882a593Smuzhiyun #define IMX8MM_CLK_NAND 119 135*4882a593Smuzhiyun #define IMX8MM_CLK_QSPI 120 136*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC1 121 137*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC2 122 138*4882a593Smuzhiyun #define IMX8MM_CLK_I2C1 123 139*4882a593Smuzhiyun #define IMX8MM_CLK_I2C2 124 140*4882a593Smuzhiyun #define IMX8MM_CLK_I2C3 125 141*4882a593Smuzhiyun #define IMX8MM_CLK_I2C4 126 142*4882a593Smuzhiyun #define IMX8MM_CLK_UART1 127 143*4882a593Smuzhiyun #define IMX8MM_CLK_UART2 128 144*4882a593Smuzhiyun #define IMX8MM_CLK_UART3 129 145*4882a593Smuzhiyun #define IMX8MM_CLK_UART4 130 146*4882a593Smuzhiyun #define IMX8MM_CLK_USB_CORE_REF 131 147*4882a593Smuzhiyun #define IMX8MM_CLK_USB_PHY_REF 132 148*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI1 133 149*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI2 134 150*4882a593Smuzhiyun #define IMX8MM_CLK_PWM1 135 151*4882a593Smuzhiyun #define IMX8MM_CLK_PWM2 136 152*4882a593Smuzhiyun #define IMX8MM_CLK_PWM3 137 153*4882a593Smuzhiyun #define IMX8MM_CLK_PWM4 138 154*4882a593Smuzhiyun #define IMX8MM_CLK_GPT1 139 155*4882a593Smuzhiyun #define IMX8MM_CLK_WDOG 140 156*4882a593Smuzhiyun #define IMX8MM_CLK_WRCLK 141 157*4882a593Smuzhiyun #define IMX8MM_CLK_DSI_CORE 142 158*4882a593Smuzhiyun #define IMX8MM_CLK_DSI_PHY_REF 143 159*4882a593Smuzhiyun #define IMX8MM_CLK_DSI_DBI 144 160*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC3 145 161*4882a593Smuzhiyun #define IMX8MM_CLK_CSI1_CORE 146 162*4882a593Smuzhiyun #define IMX8MM_CLK_CSI1_PHY_REF 147 163*4882a593Smuzhiyun #define IMX8MM_CLK_CSI1_ESC 148 164*4882a593Smuzhiyun #define IMX8MM_CLK_CSI2_CORE 149 165*4882a593Smuzhiyun #define IMX8MM_CLK_CSI2_PHY_REF 150 166*4882a593Smuzhiyun #define IMX8MM_CLK_CSI2_ESC 151 167*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE2_CTRL 152 168*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE2_PHY 153 169*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE2_AUX 154 170*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI3 155 171*4882a593Smuzhiyun #define IMX8MM_CLK_PDM 156 172*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_H1 157 173*4882a593Smuzhiyun #define IMX8MM_CLK_CLKO1 158 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI1_ROOT 159 176*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI2_ROOT 160 177*4882a593Smuzhiyun #define IMX8MM_CLK_ECSPI3_ROOT 161 178*4882a593Smuzhiyun #define IMX8MM_CLK_ENET1_ROOT 162 179*4882a593Smuzhiyun #define IMX8MM_CLK_GPT1_ROOT 163 180*4882a593Smuzhiyun #define IMX8MM_CLK_I2C1_ROOT 164 181*4882a593Smuzhiyun #define IMX8MM_CLK_I2C2_ROOT 165 182*4882a593Smuzhiyun #define IMX8MM_CLK_I2C3_ROOT 166 183*4882a593Smuzhiyun #define IMX8MM_CLK_I2C4_ROOT 167 184*4882a593Smuzhiyun #define IMX8MM_CLK_OCOTP_ROOT 168 185*4882a593Smuzhiyun #define IMX8MM_CLK_PCIE1_ROOT 169 186*4882a593Smuzhiyun #define IMX8MM_CLK_PWM1_ROOT 170 187*4882a593Smuzhiyun #define IMX8MM_CLK_PWM2_ROOT 171 188*4882a593Smuzhiyun #define IMX8MM_CLK_PWM3_ROOT 172 189*4882a593Smuzhiyun #define IMX8MM_CLK_PWM4_ROOT 173 190*4882a593Smuzhiyun #define IMX8MM_CLK_QSPI_ROOT 174 191*4882a593Smuzhiyun #define IMX8MM_CLK_NAND_ROOT 175 192*4882a593Smuzhiyun #define IMX8MM_CLK_SAI1_ROOT 176 193*4882a593Smuzhiyun #define IMX8MM_CLK_SAI1_IPG 177 194*4882a593Smuzhiyun #define IMX8MM_CLK_SAI2_ROOT 178 195*4882a593Smuzhiyun #define IMX8MM_CLK_SAI2_IPG 179 196*4882a593Smuzhiyun #define IMX8MM_CLK_SAI3_ROOT 180 197*4882a593Smuzhiyun #define IMX8MM_CLK_SAI3_IPG 181 198*4882a593Smuzhiyun #define IMX8MM_CLK_SAI4_ROOT 182 199*4882a593Smuzhiyun #define IMX8MM_CLK_SAI4_IPG 183 200*4882a593Smuzhiyun #define IMX8MM_CLK_SAI5_ROOT 184 201*4882a593Smuzhiyun #define IMX8MM_CLK_SAI5_IPG 185 202*4882a593Smuzhiyun #define IMX8MM_CLK_SAI6_ROOT 186 203*4882a593Smuzhiyun #define IMX8MM_CLK_SAI6_IPG 187 204*4882a593Smuzhiyun #define IMX8MM_CLK_UART1_ROOT 188 205*4882a593Smuzhiyun #define IMX8MM_CLK_UART2_ROOT 189 206*4882a593Smuzhiyun #define IMX8MM_CLK_UART3_ROOT 190 207*4882a593Smuzhiyun #define IMX8MM_CLK_UART4_ROOT 191 208*4882a593Smuzhiyun #define IMX8MM_CLK_USB1_CTRL_ROOT 192 209*4882a593Smuzhiyun #define IMX8MM_CLK_GPU3D_ROOT 193 210*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC1_ROOT 194 211*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC2_ROOT 195 212*4882a593Smuzhiyun #define IMX8MM_CLK_WDOG1_ROOT 196 213*4882a593Smuzhiyun #define IMX8MM_CLK_WDOG2_ROOT 197 214*4882a593Smuzhiyun #define IMX8MM_CLK_WDOG3_ROOT 198 215*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_G1_ROOT 199 216*4882a593Smuzhiyun #define IMX8MM_CLK_GPU_BUS_ROOT 200 217*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_H1_ROOT 201 218*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_G2_ROOT 202 219*4882a593Smuzhiyun #define IMX8MM_CLK_PDM_ROOT 203 220*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_ROOT 204 221*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_AXI_ROOT 205 222*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_APB_ROOT 206 223*4882a593Smuzhiyun #define IMX8MM_CLK_DISP_RTRM_ROOT 207 224*4882a593Smuzhiyun #define IMX8MM_CLK_USDHC3_ROOT 208 225*4882a593Smuzhiyun #define IMX8MM_CLK_TMU_ROOT 209 226*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_DEC_ROOT 210 227*4882a593Smuzhiyun #define IMX8MM_CLK_SDMA1_ROOT 211 228*4882a593Smuzhiyun #define IMX8MM_CLK_SDMA2_ROOT 212 229*4882a593Smuzhiyun #define IMX8MM_CLK_SDMA3_ROOT 213 230*4882a593Smuzhiyun #define IMX8MM_CLK_GPT_3M 214 231*4882a593Smuzhiyun #define IMX8MM_CLK_ARM 215 232*4882a593Smuzhiyun #define IMX8MM_CLK_PDM_IPG 216 233*4882a593Smuzhiyun #define IMX8MM_CLK_GPU2D_ROOT 217 234*4882a593Smuzhiyun #define IMX8MM_CLK_MU_ROOT 218 235*4882a593Smuzhiyun #define IMX8MM_CLK_CSI1_ROOT 219 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define IMX8MM_CLK_DRAM_CORE 220 238*4882a593Smuzhiyun #define IMX8MM_CLK_DRAM_ALT_ROOT 221 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define IMX8MM_CLK_GPIO1_ROOT 223 243*4882a593Smuzhiyun #define IMX8MM_CLK_GPIO2_ROOT 224 244*4882a593Smuzhiyun #define IMX8MM_CLK_GPIO3_ROOT 225 245*4882a593Smuzhiyun #define IMX8MM_CLK_GPIO4_ROOT 226 246*4882a593Smuzhiyun #define IMX8MM_CLK_GPIO5_ROOT 227 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun #define IMX8MM_CLK_SNVS_ROOT 228 249*4882a593Smuzhiyun #define IMX8MM_CLK_GIC 229 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_40M_CG 230 252*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_80M_CG 231 253*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_100M_CG 232 254*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_133M_CG 233 255*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_160M_CG 234 256*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_200M_CG 235 257*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_266M_CG 236 258*4882a593Smuzhiyun #define IMX8MM_SYS_PLL1_400M_CG 237 259*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_50M_CG 238 260*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_100M_CG 239 261*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_125M_CG 240 262*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_166M_CG 241 263*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_200M_CG 242 264*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_250M_CG 243 265*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_333M_CG 244 266*4882a593Smuzhiyun #define IMX8MM_SYS_PLL2_500M_CG 245 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define IMX8MM_CLK_M4_CORE 246 269*4882a593Smuzhiyun #define IMX8MM_CLK_VPU_CORE 247 270*4882a593Smuzhiyun #define IMX8MM_CLK_GPU3D_CORE 248 271*4882a593Smuzhiyun #define IMX8MM_CLK_GPU2D_CORE 249 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #define IMX8MM_CLK_CLKO2 250 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define IMX8MM_CLK_A53_CORE 251 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define IMX8MM_CLK_END 252 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun #endif 280