1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018 NXP 4*4882a593Smuzhiyun * Dong Aisheng <aisheng.dong@nxp.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* SCU Clocks */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IMX_CLK_DUMMY 0 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* CPU */ 15*4882a593Smuzhiyun #define IMX_A35_CLK 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* LSIO SS */ 18*4882a593Smuzhiyun #define IMX_LSIO_MEM_CLK 2 19*4882a593Smuzhiyun #define IMX_LSIO_BUS_CLK 3 20*4882a593Smuzhiyun #define IMX_LSIO_PWM0_CLK 10 21*4882a593Smuzhiyun #define IMX_LSIO_PWM1_CLK 11 22*4882a593Smuzhiyun #define IMX_LSIO_PWM2_CLK 12 23*4882a593Smuzhiyun #define IMX_LSIO_PWM3_CLK 13 24*4882a593Smuzhiyun #define IMX_LSIO_PWM4_CLK 14 25*4882a593Smuzhiyun #define IMX_LSIO_PWM5_CLK 15 26*4882a593Smuzhiyun #define IMX_LSIO_PWM6_CLK 16 27*4882a593Smuzhiyun #define IMX_LSIO_PWM7_CLK 17 28*4882a593Smuzhiyun #define IMX_LSIO_GPT0_CLK 18 29*4882a593Smuzhiyun #define IMX_LSIO_GPT1_CLK 19 30*4882a593Smuzhiyun #define IMX_LSIO_GPT2_CLK 20 31*4882a593Smuzhiyun #define IMX_LSIO_GPT3_CLK 21 32*4882a593Smuzhiyun #define IMX_LSIO_GPT4_CLK 22 33*4882a593Smuzhiyun #define IMX_LSIO_FSPI0_CLK 23 34*4882a593Smuzhiyun #define IMX_LSIO_FSPI1_CLK 24 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Connectivity SS */ 37*4882a593Smuzhiyun #define IMX_CONN_AXI_CLK_ROOT 30 38*4882a593Smuzhiyun #define IMX_CONN_AHB_CLK_ROOT 31 39*4882a593Smuzhiyun #define IMX_CONN_IPG_CLK_ROOT 32 40*4882a593Smuzhiyun #define IMX_CONN_SDHC0_CLK 40 41*4882a593Smuzhiyun #define IMX_CONN_SDHC1_CLK 41 42*4882a593Smuzhiyun #define IMX_CONN_SDHC2_CLK 42 43*4882a593Smuzhiyun #define IMX_CONN_ENET0_ROOT_CLK 43 44*4882a593Smuzhiyun #define IMX_CONN_ENET0_BYPASS_CLK 44 45*4882a593Smuzhiyun #define IMX_CONN_ENET0_RGMII_CLK 45 46*4882a593Smuzhiyun #define IMX_CONN_ENET1_ROOT_CLK 46 47*4882a593Smuzhiyun #define IMX_CONN_ENET1_BYPASS_CLK 47 48*4882a593Smuzhiyun #define IMX_CONN_ENET1_RGMII_CLK 48 49*4882a593Smuzhiyun #define IMX_CONN_GPMI_BCH_IO_CLK 49 50*4882a593Smuzhiyun #define IMX_CONN_GPMI_BCH_CLK 50 51*4882a593Smuzhiyun #define IMX_CONN_USB2_ACLK 51 52*4882a593Smuzhiyun #define IMX_CONN_USB2_BUS_CLK 52 53*4882a593Smuzhiyun #define IMX_CONN_USB2_LPM_CLK 53 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* HSIO SS */ 56*4882a593Smuzhiyun #define IMX_HSIO_AXI_CLK 60 57*4882a593Smuzhiyun #define IMX_HSIO_PER_CLK 61 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Display controller SS */ 60*4882a593Smuzhiyun #define IMX_DC_AXI_EXT_CLK 70 61*4882a593Smuzhiyun #define IMX_DC_AXI_INT_CLK 71 62*4882a593Smuzhiyun #define IMX_DC_CFG_CLK 72 63*4882a593Smuzhiyun #define IMX_DC0_PLL0_CLK 80 64*4882a593Smuzhiyun #define IMX_DC0_PLL1_CLK 81 65*4882a593Smuzhiyun #define IMX_DC0_DISP0_CLK 82 66*4882a593Smuzhiyun #define IMX_DC0_DISP1_CLK 83 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* MIPI-LVDS SS */ 69*4882a593Smuzhiyun #define IMX_MIPI_IPG_CLK 90 70*4882a593Smuzhiyun #define IMX_MIPI0_PIXEL_CLK 100 71*4882a593Smuzhiyun #define IMX_MIPI0_BYPASS_CLK 101 72*4882a593Smuzhiyun #define IMX_MIPI0_LVDS_PIXEL_CLK 102 73*4882a593Smuzhiyun #define IMX_MIPI0_LVDS_BYPASS_CLK 103 74*4882a593Smuzhiyun #define IMX_MIPI0_LVDS_PHY_CLK 104 75*4882a593Smuzhiyun #define IMX_MIPI0_I2C0_CLK 105 76*4882a593Smuzhiyun #define IMX_MIPI0_I2C1_CLK 106 77*4882a593Smuzhiyun #define IMX_MIPI0_PWM0_CLK 107 78*4882a593Smuzhiyun #define IMX_MIPI1_PIXEL_CLK 108 79*4882a593Smuzhiyun #define IMX_MIPI1_BYPASS_CLK 109 80*4882a593Smuzhiyun #define IMX_MIPI1_LVDS_PIXEL_CLK 110 81*4882a593Smuzhiyun #define IMX_MIPI1_LVDS_BYPASS_CLK 111 82*4882a593Smuzhiyun #define IMX_MIPI1_LVDS_PHY_CLK 112 83*4882a593Smuzhiyun #define IMX_MIPI1_I2C0_CLK 113 84*4882a593Smuzhiyun #define IMX_MIPI1_I2C1_CLK 114 85*4882a593Smuzhiyun #define IMX_MIPI1_PWM0_CLK 115 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* IMG SS */ 88*4882a593Smuzhiyun #define IMX_IMG_AXI_CLK 120 89*4882a593Smuzhiyun #define IMX_IMG_IPG_CLK 121 90*4882a593Smuzhiyun #define IMX_IMG_PXL_CLK 122 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* MIPI-CSI SS */ 93*4882a593Smuzhiyun #define IMX_CSI0_CORE_CLK 130 94*4882a593Smuzhiyun #define IMX_CSI0_ESC_CLK 131 95*4882a593Smuzhiyun #define IMX_CSI0_PWM0_CLK 132 96*4882a593Smuzhiyun #define IMX_CSI0_I2C0_CLK 133 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* PARALLER CSI SS */ 99*4882a593Smuzhiyun #define IMX_PARALLEL_CSI_DPLL_CLK 140 100*4882a593Smuzhiyun #define IMX_PARALLEL_CSI_PIXEL_CLK 141 101*4882a593Smuzhiyun #define IMX_PARALLEL_CSI_MCLK_CLK 142 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* VPU SS */ 104*4882a593Smuzhiyun #define IMX_VPU_ENC_CLK 150 105*4882a593Smuzhiyun #define IMX_VPU_DEC_CLK 151 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* GPU SS */ 108*4882a593Smuzhiyun #define IMX_GPU0_CORE_CLK 160 109*4882a593Smuzhiyun #define IMX_GPU0_SHADER_CLK 161 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* ADMA SS */ 112*4882a593Smuzhiyun #define IMX_ADMA_IPG_CLK_ROOT 165 113*4882a593Smuzhiyun #define IMX_ADMA_UART0_CLK 170 114*4882a593Smuzhiyun #define IMX_ADMA_UART1_CLK 171 115*4882a593Smuzhiyun #define IMX_ADMA_UART2_CLK 172 116*4882a593Smuzhiyun #define IMX_ADMA_UART3_CLK 173 117*4882a593Smuzhiyun #define IMX_ADMA_SPI0_CLK 174 118*4882a593Smuzhiyun #define IMX_ADMA_SPI1_CLK 175 119*4882a593Smuzhiyun #define IMX_ADMA_SPI2_CLK 176 120*4882a593Smuzhiyun #define IMX_ADMA_SPI3_CLK 177 121*4882a593Smuzhiyun #define IMX_ADMA_CAN0_CLK 178 122*4882a593Smuzhiyun #define IMX_ADMA_CAN1_CLK 179 123*4882a593Smuzhiyun #define IMX_ADMA_CAN2_CLK 180 124*4882a593Smuzhiyun #define IMX_ADMA_I2C0_CLK 181 125*4882a593Smuzhiyun #define IMX_ADMA_I2C1_CLK 182 126*4882a593Smuzhiyun #define IMX_ADMA_I2C2_CLK 183 127*4882a593Smuzhiyun #define IMX_ADMA_I2C3_CLK 184 128*4882a593Smuzhiyun #define IMX_ADMA_FTM0_CLK 185 129*4882a593Smuzhiyun #define IMX_ADMA_FTM1_CLK 186 130*4882a593Smuzhiyun #define IMX_ADMA_ADC0_CLK 187 131*4882a593Smuzhiyun #define IMX_ADMA_PWM_CLK 188 132*4882a593Smuzhiyun #define IMX_ADMA_LCD_CLK 189 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define IMX_SCU_CLK_END 190 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* LPCG clocks */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* LSIO SS LPCG */ 139*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 140*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 141*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 142*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 143*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 144*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 145*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 146*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 147*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 148*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 149*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 150*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 151*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 152*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 153*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 154*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 155*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 156*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 157*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 158*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 159*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 160*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 161*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 162*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 163*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 164*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 165*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 166*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 167*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 168*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 169*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 170*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 171*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 172*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 173*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 174*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 175*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 176*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 177*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 178*4882a593Smuzhiyun #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 179*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 180*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 181*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 182*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 183*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 184*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 185*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 186*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 187*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 188*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 189*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 190*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 191*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 192*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 193*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 194*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 195*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 196*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 197*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 198*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 199*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 200*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 201*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 202*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 203*4882a593Smuzhiyun #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 204*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI0_HCLK 65 205*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 206*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 207*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 208*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI1_HCLK 69 209*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 210*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 211*4882a593Smuzhiyun #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define IMX_LSIO_LPCG_CLK_END 73 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* Connectivity SS LPCG */ 216*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 217*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC0_PER_CLK 1 218*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC0_HCLK 2 219*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 220*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC1_PER_CLK 4 221*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC1_HCLK 5 222*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 223*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC2_PER_CLK 7 224*4882a593Smuzhiyun #define IMX_CONN_LPCG_SDHC2_HCLK 8 225*4882a593Smuzhiyun #define IMX_CONN_LPCG_GPMI_APB_CLK 9 226*4882a593Smuzhiyun #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 227*4882a593Smuzhiyun #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 228*4882a593Smuzhiyun #define IMX_CONN_LPCG_GPMI_BCH_CLK 12 229*4882a593Smuzhiyun #define IMX_CONN_LPCG_APBHDMA_CLK 13 230*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 231*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET0_TX_CLK 15 232*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET0_AHB_CLK 16 233*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 234*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET0_IPG_CLK 18 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 237*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET1_TX_CLK 20 238*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET1_AHB_CLK 21 239*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 240*4882a593Smuzhiyun #define IMX_CONN_LPCG_ENET1_IPG_CLK 23 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define IMX_CONN_LPCG_CLK_END 24 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* ADMA SS LPCG */ 245*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART0_IPG_CLK 0 246*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 247*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART1_IPG_CLK 2 248*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 249*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART2_IPG_CLK 4 250*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 251*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART3_IPG_CLK 6 252*4882a593Smuzhiyun #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 253*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 254*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 255*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 256*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 257*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI0_CLK 12 258*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI1_CLK 13 259*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI2_CLK 14 260*4882a593Smuzhiyun #define IMX_ADMA_LPCG_SPI3_CLK 15 261*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 262*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 263*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 264*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 265*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 266*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 267*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 268*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 269*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 270*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C0_CLK 25 271*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C1_CLK 26 272*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C2_CLK 27 273*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C3_CLK 28 274*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 275*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 276*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 277*4882a593Smuzhiyun #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 278*4882a593Smuzhiyun #define IMX_ADMA_LPCG_FTM0_CLK 33 279*4882a593Smuzhiyun #define IMX_ADMA_LPCG_FTM1_CLK 34 280*4882a593Smuzhiyun #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 281*4882a593Smuzhiyun #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 282*4882a593Smuzhiyun #define IMX_ADMA_LPCG_PWM_HI_CLK 37 283*4882a593Smuzhiyun #define IMX_ADMA_LPCG_PWM_IPG_CLK 38 284*4882a593Smuzhiyun #define IMX_ADMA_LPCG_LCD_PIX_CLK 39 285*4882a593Smuzhiyun #define IMX_ADMA_LPCG_LCD_APB_CLK 40 286*4882a593Smuzhiyun #define IMX_ADMA_LPCG_DSP_ADB_CLK 41 287*4882a593Smuzhiyun #define IMX_ADMA_LPCG_DSP_IPG_CLK 42 288*4882a593Smuzhiyun #define IMX_ADMA_LPCG_DSP_CORE_CLK 43 289*4882a593Smuzhiyun #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define IMX_ADMA_LPCG_CLK_END 45 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX_H */ 294