1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX7D_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX7D_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX7D_OSC_24M_CLK 0 10*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN 1 11*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_CLK 2 12*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_SRC 3 13*4882a593Smuzhiyun #define IMX7D_PLL_ARM_MAIN_BYPASS 4 14*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN 5 15*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_CLK 6 16*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_SRC 7 17*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_BYPASS 8 18*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_480M 9 19*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_240M 10 20*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_120M 11 21*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_480M_CLK 12 22*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_240M_CLK 13 23*4882a593Smuzhiyun #define IMX7D_PLL_SYS_MAIN_120M_CLK 14 24*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_392M_CLK 15 25*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_196M 16 26*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD0_196M_CLK 17 27*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_332M_CLK 18 28*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_166M 19 29*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD1_166M_CLK 20 30*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_270M_CLK 21 31*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_135M 22 32*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD2_135M_CLK 23 33*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD3_CLK 24 34*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD4_CLK 25 35*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD5_CLK 26 36*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD6_CLK 27 37*4882a593Smuzhiyun #define IMX7D_PLL_SYS_PFD7_CLK 28 38*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN 29 39*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_CLK 30 40*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_SRC 31 41*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_BYPASS 32 42*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_500M 33 43*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_250M 34 44*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_125M 35 45*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_100M 36 46*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_50M 37 47*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_40M 38 48*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_25M 39 49*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_500M_CLK 40 50*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 51*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 52*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 53*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_50M_CLK 44 54*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_40M_CLK 45 55*4882a593Smuzhiyun #define IMX7D_PLL_ENET_MAIN_25M_CLK 46 56*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN 47 57*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_CLK 48 58*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_SRC 49 59*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_BYPASS 50 60*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_533M 51 61*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 62*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN 53 63*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_CLK 54 64*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_SRC 55 65*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 66*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_CLK 57 67*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN 58 68*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_SRC 59 69*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 70*4882a593Smuzhiyun #define IMX7D_USB_MAIN_480M_CLK 61 71*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_CLK 62 72*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_SRC 63 73*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_CG 64 74*4882a593Smuzhiyun #define IMX7D_ARM_A7_ROOT_DIV 65 75*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_CLK 66 76*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_SRC 67 77*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_CG 68 78*4882a593Smuzhiyun #define IMX7D_ARM_M4_ROOT_DIV 69 79*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ 80*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ 81*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ 82*4882a593Smuzhiyun #define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ 83*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_CLK 74 84*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_SRC 75 85*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_CG 76 86*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_DIV 77 87*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_CLK 78 88*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_SRC 79 89*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_CG 80 90*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_DIV 81 91*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_CLK 82 92*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_SRC 83 93*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_CG 84 94*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_DIV 85 95*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 96*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 97*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 98*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 99*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_CLK 90 100*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_SRC 91 101*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_CG 92 102*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_DIV 93 103*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_CLK 94 104*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_SRC 95 105*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_CG 96 106*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ROOT_DIV 97 107*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_CLK 98 108*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_SRC 99 109*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_CG 100 110*4882a593Smuzhiyun #define IMX7D_DRAM_ROOT_DIV 101 111*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 112*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 113*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 114*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 115*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_CLK 106 116*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_SRC 107 117*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_CG 108 118*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_DIV 109 119*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_CLK 110 120*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_SRC 111 121*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_CG 112 122*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_DIV 113 123*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_CLK 114 124*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_SRC 115 125*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_CG 116 126*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_DIV 117 127*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_CLK 118 128*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_SRC 119 129*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_CG 120 130*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_DIV 121 131*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_CLK 122 132*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_SRC 123 133*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_CG 124 134*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_DIV 125 135*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 136*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 137*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_CG 128 138*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 139*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_CLK 130 140*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_SRC 131 141*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_CG 132 142*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_DIV 133 143*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_CLK 134 144*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_SRC 135 145*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_CG 136 146*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_DIV 137 147*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_CLK 138 148*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_SRC 139 149*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_CG 140 150*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_DIV 141 151*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_CLK 142 152*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_SRC 143 153*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_CG 144 154*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_DIV 145 155*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_CLK 146 156*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_SRC 147 157*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_CG 148 158*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_DIV 149 159*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_CLK 150 160*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_SRC 151 161*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_CG 152 162*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_DIV 153 163*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_CLK 154 164*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_SRC 155 165*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_CG 156 166*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_DIV 157 167*4882a593Smuzhiyun #define IMX7D_ENET1_IPG_ROOT_CLK 158 168*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_SRC 159 169*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_CG 160 170*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_DIV 161 171*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_CLK 162 172*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_SRC 163 173*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_CG 164 174*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_DIV 165 175*4882a593Smuzhiyun #define IMX7D_ENET2_IPG_ROOT_CLK 166 176*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_SRC 167 177*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_CG 168 178*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_DIV 169 179*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_CLK 170 180*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_SRC 171 181*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_CG 172 182*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_DIV 173 183*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_CLK 174 184*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_SRC 175 185*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_CG 176 186*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_DIV 177 187*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_CLK 178 188*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_SRC 179 189*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_CG 180 190*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_DIV 181 191*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_CLK 182 192*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_SRC 183 193*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_CG 184 194*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_DIV 185 195*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_CLK 186 196*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_SRC 187 197*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_CG 188 198*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_DIV 189 199*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_CLK 190 200*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_SRC 191 201*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_CG 192 202*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_DIV 193 203*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_CLK 194 204*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_SRC 195 205*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_CG 196 206*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_DIV 197 207*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_CLK 198 208*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_SRC 199 209*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_CG 200 210*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_DIV 201 211*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_CLK 202 212*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_SRC 203 213*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_CG 204 214*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_DIV 205 215*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_CLK 206 216*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_SRC 207 217*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_CG 208 218*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_DIV 209 219*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_CLK 210 220*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_SRC 211 221*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_CG 212 222*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_DIV 213 223*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_CLK 214 224*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_SRC 215 225*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_CG 216 226*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_DIV 217 227*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_CLK 218 228*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_SRC 219 229*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_CG 220 230*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_DIV 221 231*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_CLK 222 232*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_SRC 223 233*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_CG 224 234*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_DIV 225 235*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_CLK 226 236*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_SRC 227 237*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_CG 228 238*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_DIV 229 239*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_CLK 230 240*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_SRC 231 241*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_CG 232 242*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_DIV 233 243*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_CLK 234 244*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_SRC 235 245*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_CG 236 246*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_DIV 237 247*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_CLK 238 248*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_SRC 239 249*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_CG 240 250*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_DIV 241 251*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_CLK 242 252*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_SRC 243 253*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_CG 244 254*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_DIV 245 255*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_CLK 246 256*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_SRC 247 257*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_CG 248 258*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_DIV 249 259*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_CLK 250 260*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_SRC 251 261*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_CG 252 262*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_DIV 253 263*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_CLK 254 264*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_SRC 255 265*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_CG 256 266*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_DIV 257 267*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_CLK 258 268*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_SRC 259 269*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_CG 260 270*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_DIV 261 271*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_CLK 262 272*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_SRC 263 273*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_CG 264 274*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_DIV 265 275*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_CLK 266 276*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_SRC 267 277*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_CG 268 278*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_DIV 269 279*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_CLK 270 280*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_SRC 271 281*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_CG 272 282*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_DIV 273 283*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_CLK 274 284*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_SRC 275 285*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_CG 276 286*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_DIV 277 287*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_CLK 278 288*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_SRC 279 289*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_CG 280 290*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_DIV 281 291*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_CLK 282 292*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_SRC 283 293*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_CG 284 294*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_DIV 285 295*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_CLK 286 296*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_SRC 287 297*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_CG 288 298*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_DIV 289 299*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_CLK 290 300*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_SRC 291 301*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_CG 292 302*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_DIV 293 303*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_CLK 294 304*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_SRC 295 305*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_CG 296 306*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_DIV 297 307*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_CLK 298 308*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_SRC 299 309*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_CG 300 310*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_DIV 301 311*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_CLK 302 312*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_SRC 303 313*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_CG 304 314*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_DIV 305 315*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_CLK 306 316*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_SRC 307 317*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_CG 308 318*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_DIV 309 319*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_CLK 310 320*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_SRC 311 321*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_CG 312 322*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_DIV 313 323*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_CLK 314 324*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_SRC 315 325*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_CG 316 326*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_DIV 317 327*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_CLK 318 328*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_SRC 319 329*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_CG 320 330*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_DIV 321 331*4882a593Smuzhiyun #define IMX7D_WDOG1_ROOT_CLK 322 332*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_SRC 323 333*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_CG 324 334*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_DIV 325 335*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_CLK 326 336*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_SRC 327 337*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_CG 328 338*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_DIV 329 339*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_CLK 330 340*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_SRC 331 341*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_CG 332 342*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_DIV 333 343*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_CLK 334 344*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_SRC 335 345*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_CG 336 346*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_DIV 337 347*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_SRC 338 348*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_CG 339 349*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_DIV 340 350*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_SRC 341 351*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_CG 342 352*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_DIV 343 353*4882a593Smuzhiyun #define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 354*4882a593Smuzhiyun #define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 355*4882a593Smuzhiyun #define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 356*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 357*4882a593Smuzhiyun #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 358*4882a593Smuzhiyun #define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 359*4882a593Smuzhiyun #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 360*4882a593Smuzhiyun #define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 361*4882a593Smuzhiyun #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 362*4882a593Smuzhiyun #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 363*4882a593Smuzhiyun #define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 364*4882a593Smuzhiyun #define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 365*4882a593Smuzhiyun #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 366*4882a593Smuzhiyun #define IMX7D_SAI1_ROOT_PRE_DIV 357 367*4882a593Smuzhiyun #define IMX7D_SAI2_ROOT_PRE_DIV 358 368*4882a593Smuzhiyun #define IMX7D_SAI3_ROOT_PRE_DIV 359 369*4882a593Smuzhiyun #define IMX7D_SPDIF_ROOT_PRE_DIV 360 370*4882a593Smuzhiyun #define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 371*4882a593Smuzhiyun #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 372*4882a593Smuzhiyun #define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 373*4882a593Smuzhiyun #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 374*4882a593Smuzhiyun #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 375*4882a593Smuzhiyun #define IMX7D_EIM_ROOT_PRE_DIV 366 376*4882a593Smuzhiyun #define IMX7D_NAND_ROOT_PRE_DIV 367 377*4882a593Smuzhiyun #define IMX7D_QSPI_ROOT_PRE_DIV 368 378*4882a593Smuzhiyun #define IMX7D_USDHC1_ROOT_PRE_DIV 369 379*4882a593Smuzhiyun #define IMX7D_USDHC2_ROOT_PRE_DIV 370 380*4882a593Smuzhiyun #define IMX7D_USDHC3_ROOT_PRE_DIV 371 381*4882a593Smuzhiyun #define IMX7D_CAN1_ROOT_PRE_DIV 372 382*4882a593Smuzhiyun #define IMX7D_CAN2_ROOT_PRE_DIV 373 383*4882a593Smuzhiyun #define IMX7D_I2C1_ROOT_PRE_DIV 374 384*4882a593Smuzhiyun #define IMX7D_I2C2_ROOT_PRE_DIV 375 385*4882a593Smuzhiyun #define IMX7D_I2C3_ROOT_PRE_DIV 376 386*4882a593Smuzhiyun #define IMX7D_I2C4_ROOT_PRE_DIV 377 387*4882a593Smuzhiyun #define IMX7D_UART1_ROOT_PRE_DIV 378 388*4882a593Smuzhiyun #define IMX7D_UART2_ROOT_PRE_DIV 379 389*4882a593Smuzhiyun #define IMX7D_UART3_ROOT_PRE_DIV 380 390*4882a593Smuzhiyun #define IMX7D_UART4_ROOT_PRE_DIV 381 391*4882a593Smuzhiyun #define IMX7D_UART5_ROOT_PRE_DIV 382 392*4882a593Smuzhiyun #define IMX7D_UART6_ROOT_PRE_DIV 383 393*4882a593Smuzhiyun #define IMX7D_UART7_ROOT_PRE_DIV 384 394*4882a593Smuzhiyun #define IMX7D_ECSPI1_ROOT_PRE_DIV 385 395*4882a593Smuzhiyun #define IMX7D_ECSPI2_ROOT_PRE_DIV 386 396*4882a593Smuzhiyun #define IMX7D_ECSPI3_ROOT_PRE_DIV 387 397*4882a593Smuzhiyun #define IMX7D_ECSPI4_ROOT_PRE_DIV 388 398*4882a593Smuzhiyun #define IMX7D_PWM1_ROOT_PRE_DIV 389 399*4882a593Smuzhiyun #define IMX7D_PWM2_ROOT_PRE_DIV 390 400*4882a593Smuzhiyun #define IMX7D_PWM3_ROOT_PRE_DIV 391 401*4882a593Smuzhiyun #define IMX7D_PWM4_ROOT_PRE_DIV 392 402*4882a593Smuzhiyun #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 403*4882a593Smuzhiyun #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 404*4882a593Smuzhiyun #define IMX7D_SIM1_ROOT_PRE_DIV 395 405*4882a593Smuzhiyun #define IMX7D_SIM2_ROOT_PRE_DIV 396 406*4882a593Smuzhiyun #define IMX7D_GPT1_ROOT_PRE_DIV 397 407*4882a593Smuzhiyun #define IMX7D_GPT2_ROOT_PRE_DIV 398 408*4882a593Smuzhiyun #define IMX7D_GPT3_ROOT_PRE_DIV 399 409*4882a593Smuzhiyun #define IMX7D_GPT4_ROOT_PRE_DIV 400 410*4882a593Smuzhiyun #define IMX7D_TRACE_ROOT_PRE_DIV 401 411*4882a593Smuzhiyun #define IMX7D_WDOG_ROOT_PRE_DIV 402 412*4882a593Smuzhiyun #define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 413*4882a593Smuzhiyun #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 414*4882a593Smuzhiyun #define IMX7D_WRCLK_ROOT_PRE_DIV 405 415*4882a593Smuzhiyun #define IMX7D_CLKO1_ROOT_PRE_DIV 406 416*4882a593Smuzhiyun #define IMX7D_CLKO2_ROOT_PRE_DIV 407 417*4882a593Smuzhiyun #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 418*4882a593Smuzhiyun #define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 419*4882a593Smuzhiyun #define IMX7D_LVDS1_IN_CLK 410 420*4882a593Smuzhiyun #define IMX7D_LVDS1_OUT_SEL 411 421*4882a593Smuzhiyun #define IMX7D_LVDS1_OUT_CLK 412 422*4882a593Smuzhiyun #define IMX7D_CLK_DUMMY 413 423*4882a593Smuzhiyun #define IMX7D_GPT_3M_CLK 414 424*4882a593Smuzhiyun #define IMX7D_OCRAM_CLK 415 425*4882a593Smuzhiyun #define IMX7D_OCRAM_S_CLK 416 426*4882a593Smuzhiyun #define IMX7D_WDOG2_ROOT_CLK 417 427*4882a593Smuzhiyun #define IMX7D_WDOG3_ROOT_CLK 418 428*4882a593Smuzhiyun #define IMX7D_WDOG4_ROOT_CLK 419 429*4882a593Smuzhiyun #define IMX7D_SDMA_CORE_CLK 420 430*4882a593Smuzhiyun #define IMX7D_USB1_MAIN_480M_CLK 421 431*4882a593Smuzhiyun #define IMX7D_USB_CTRL_CLK 422 432*4882a593Smuzhiyun #define IMX7D_USB_PHY1_CLK 423 433*4882a593Smuzhiyun #define IMX7D_USB_PHY2_CLK 424 434*4882a593Smuzhiyun #define IMX7D_IPG_ROOT_CLK 425 435*4882a593Smuzhiyun #define IMX7D_SAI1_IPG_CLK 426 436*4882a593Smuzhiyun #define IMX7D_SAI2_IPG_CLK 427 437*4882a593Smuzhiyun #define IMX7D_SAI3_IPG_CLK 428 438*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_TEST_DIV 429 439*4882a593Smuzhiyun #define IMX7D_PLL_AUDIO_POST_DIV 430 440*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_TEST_DIV 431 441*4882a593Smuzhiyun #define IMX7D_PLL_VIDEO_POST_DIV 432 442*4882a593Smuzhiyun #define IMX7D_MU_ROOT_CLK 433 443*4882a593Smuzhiyun #define IMX7D_SEMA4_HS_ROOT_CLK 434 444*4882a593Smuzhiyun #define IMX7D_PLL_DRAM_TEST_DIV 435 445*4882a593Smuzhiyun #define IMX7D_ADC_ROOT_CLK 436 446*4882a593Smuzhiyun #define IMX7D_CLK_ARM 437 447*4882a593Smuzhiyun #define IMX7D_CKIL 438 448*4882a593Smuzhiyun #define IMX7D_OCOTP_CLK 439 449*4882a593Smuzhiyun #define IMX7D_NAND_RAWNAND_CLK 440 450*4882a593Smuzhiyun #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 451*4882a593Smuzhiyun #define IMX7D_SNVS_CLK 442 452*4882a593Smuzhiyun #define IMX7D_CAAM_CLK 443 453*4882a593Smuzhiyun #define IMX7D_KPP_ROOT_CLK 444 454*4882a593Smuzhiyun #define IMX7D_PXP_CLK 445 455*4882a593Smuzhiyun #define IMX7D_CLK_END 446 456*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 457