1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017-2018 NXP. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6SLL_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IMX6SLL_CLK_DUMMY 0 12*4882a593Smuzhiyun #define IMX6SLL_CLK_CKIL 1 13*4882a593Smuzhiyun #define IMX6SLL_CLK_OSC 2 14*4882a593Smuzhiyun #define IMX6SLL_PLL1_BYPASS_SRC 3 15*4882a593Smuzhiyun #define IMX6SLL_PLL2_BYPASS_SRC 4 16*4882a593Smuzhiyun #define IMX6SLL_PLL3_BYPASS_SRC 5 17*4882a593Smuzhiyun #define IMX6SLL_PLL4_BYPASS_SRC 6 18*4882a593Smuzhiyun #define IMX6SLL_PLL5_BYPASS_SRC 7 19*4882a593Smuzhiyun #define IMX6SLL_PLL6_BYPASS_SRC 8 20*4882a593Smuzhiyun #define IMX6SLL_PLL7_BYPASS_SRC 9 21*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1 10 22*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2 11 23*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3 12 24*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4 13 25*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5 14 26*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL6 15 27*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL7 16 28*4882a593Smuzhiyun #define IMX6SLL_PLL1_BYPASS 17 29*4882a593Smuzhiyun #define IMX6SLL_PLL2_BYPASS 18 30*4882a593Smuzhiyun #define IMX6SLL_PLL3_BYPASS 19 31*4882a593Smuzhiyun #define IMX6SLL_PLL4_BYPASS 20 32*4882a593Smuzhiyun #define IMX6SLL_PLL5_BYPASS 21 33*4882a593Smuzhiyun #define IMX6SLL_PLL6_BYPASS 22 34*4882a593Smuzhiyun #define IMX6SLL_PLL7_BYPASS 23 35*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1_SYS 24 36*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_BUS 25 37*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_USB_OTG 26 38*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_AUDIO 27 39*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_VIDEO 28 40*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL6_ENET 29 41*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL7_USB_HOST 30 42*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY1 31 43*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY2 32 44*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY1_GATE 33 45*4882a593Smuzhiyun #define IMX6SLL_CLK_USBPHY2_GATE 34 46*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD0 35 47*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD1 36 48*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD2 37 49*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_PFD3 38 50*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD0 39 51*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD1 40 52*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD2 41 53*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_PFD3 42 54*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_POST_DIV 43 55*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 56*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_POST_DIV 45 57*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 58*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL2_198M 47 59*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_120M 48 60*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_80M 49 61*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL3_60M 50 62*4882a593Smuzhiyun #define IMX6SLL_CLK_STEP 51 63*4882a593Smuzhiyun #define IMX6SLL_CLK_PLL1_SW 52 64*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_ALT_SEL 53 65*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_SEL 54 66*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_PRE 55 67*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_PRE 56 68*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 69*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 70*4882a593Smuzhiyun #define IMX6SLL_CLK_PERCLK_SEL 59 71*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1_SEL 60 72*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2_SEL 61 73*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3_SEL 62 74*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_SEL 63 75*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_SEL 64 76*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_SEL 65 77*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP_SEL 66 78*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PRE_SEL 67 79*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_SEL 68 80*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PRE_SEL 69 81*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_SEL 70 82*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI_SEL 71 83*4882a593Smuzhiyun #define IMX6SLL_CLK_UART_SEL 72 84*4882a593Smuzhiyun #define IMX6SLL_CLK_ARM 73 85*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH 74 86*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2 75 87*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH2_CLK2 76 88*4882a593Smuzhiyun #define IMX6SLL_CLK_PERIPH_CLK2 77 89*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_PODF 78 90*4882a593Smuzhiyun #define IMX6SLL_CLK_AXI_PODF 79 91*4882a593Smuzhiyun #define IMX6SLL_CLK_AHB 80 92*4882a593Smuzhiyun #define IMX6SLL_CLK_IPG 81 93*4882a593Smuzhiyun #define IMX6SLL_CLK_PERCLK 82 94*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1_PODF 83 95*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2_PODF 84 96*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3_PODF 85 97*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_PRED 86 98*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_PRED 87 99*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_PRED 88 100*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_PODF 89 101*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_PODF 90 102*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_PODF 91 103*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP_PODF 92 104*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PRED 93 105*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PODF 94 106*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_SEL 95 107*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PODF 96 108*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_PRED 97 109*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_PODF 98 110*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI_PODF 99 111*4882a593Smuzhiyun #define IMX6SLL_CLK_UART_PODF 100 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* CCGR 0 */ 114*4882a593Smuzhiyun #define IMX6SLL_CLK_AIPSTZ1 101 115*4882a593Smuzhiyun #define IMX6SLL_CLK_AIPSTZ2 102 116*4882a593Smuzhiyun #define IMX6SLL_CLK_DCP 103 117*4882a593Smuzhiyun #define IMX6SLL_CLK_UART2_IPG 104 118*4882a593Smuzhiyun #define IMX6SLL_CLK_UART2_SERIAL 105 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* CCGR 1 */ 121*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI1 106 122*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI2 107 123*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI3 108 124*4882a593Smuzhiyun #define IMX6SLL_CLK_ECSPI4 109 125*4882a593Smuzhiyun #define IMX6SLL_CLK_UART3_IPG 110 126*4882a593Smuzhiyun #define IMX6SLL_CLK_UART3_SERIAL 111 127*4882a593Smuzhiyun #define IMX6SLL_CLK_UART4_IPG 112 128*4882a593Smuzhiyun #define IMX6SLL_CLK_UART4_SERIAL 113 129*4882a593Smuzhiyun #define IMX6SLL_CLK_EPIT1 114 130*4882a593Smuzhiyun #define IMX6SLL_CLK_EPIT2 115 131*4882a593Smuzhiyun #define IMX6SLL_CLK_GPT_BUS 116 132*4882a593Smuzhiyun #define IMX6SLL_CLK_GPT_SERIAL 117 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* CCGR2 */ 135*4882a593Smuzhiyun #define IMX6SLL_CLK_CSI 118 136*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C1 119 137*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C2 120 138*4882a593Smuzhiyun #define IMX6SLL_CLK_I2C3 121 139*4882a593Smuzhiyun #define IMX6SLL_CLK_OCOTP 122 140*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_APB 123 141*4882a593Smuzhiyun #define IMX6SLL_CLK_PXP 124 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* CCGR3 */ 144*4882a593Smuzhiyun #define IMX6SLL_CLK_UART5_IPG 125 145*4882a593Smuzhiyun #define IMX6SLL_CLK_UART5_SERIAL 126 146*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_AXI 127 147*4882a593Smuzhiyun #define IMX6SLL_CLK_EPDC_PIX 128 148*4882a593Smuzhiyun #define IMX6SLL_CLK_LCDIF_PIX 129 149*4882a593Smuzhiyun #define IMX6SLL_CLK_WDOG1 130 150*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_P0_FAST 131 151*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_P0_IPG 132 152*4882a593Smuzhiyun #define IMX6SLL_CLK_OCRAM 133 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* CCGR4 */ 155*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM1 134 156*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM2 135 157*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM3 136 158*4882a593Smuzhiyun #define IMX6SLL_CLK_PWM4 137 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* CCGR 5 */ 161*4882a593Smuzhiyun #define IMX6SLL_CLK_ROM 138 162*4882a593Smuzhiyun #define IMX6SLL_CLK_SDMA 139 163*4882a593Smuzhiyun #define IMX6SLL_CLK_KPP 140 164*4882a593Smuzhiyun #define IMX6SLL_CLK_WDOG2 141 165*4882a593Smuzhiyun #define IMX6SLL_CLK_SPBA 142 166*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF 143 167*4882a593Smuzhiyun #define IMX6SLL_CLK_SPDIF_GCLK 144 168*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1 145 169*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI1_IPG 146 170*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2 147 171*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI2_IPG 148 172*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3 149 173*4882a593Smuzhiyun #define IMX6SLL_CLK_SSI3_IPG 150 174*4882a593Smuzhiyun #define IMX6SLL_CLK_UART1_IPG 151 175*4882a593Smuzhiyun #define IMX6SLL_CLK_UART1_SERIAL 152 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* CCGR 6 */ 178*4882a593Smuzhiyun #define IMX6SLL_CLK_USBOH3 153 179*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC1 154 180*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC2 155 181*4882a593Smuzhiyun #define IMX6SLL_CLK_USDHC3 156 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define IMX6SLL_CLK_IPP_DI0 157 184*4882a593Smuzhiyun #define IMX6SLL_CLK_IPP_DI1 158 185*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_SEL 159 186*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 187*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_7 161 188*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 189*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI0 163 190*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_SEL 164 191*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 192*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_7 166 193*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 194*4882a593Smuzhiyun #define IMX6SLL_CLK_LDB_DI1 168 195*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 196*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 197*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 198*4882a593Smuzhiyun #define IMX6SLL_CLK_EXTERN_AUDIO 172 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO1 173 201*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO2 174 202*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO3 175 203*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO4 176 204*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO5 177 205*4882a593Smuzhiyun #define IMX6SLL_CLK_GPIO6 178 206*4882a593Smuzhiyun #define IMX6SLL_CLK_MMDC_P1_IPG 179 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define IMX6SLL_CLK_END 180 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ 211