1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX6SL_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX6SL_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX6SL_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX6SL_CLK_CKIL 1 11*4882a593Smuzhiyun #define IMX6SL_CLK_OSC 2 12*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1_SYS 3 13*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_BUS 4 14*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_USB_OTG 5 15*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_AUDIO 6 16*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_VIDEO 7 17*4882a593Smuzhiyun #define IMX6SL_CLK_PLL6_ENET 8 18*4882a593Smuzhiyun #define IMX6SL_CLK_PLL7_USB_HOST 9 19*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY1 10 20*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY2 11 21*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY1_GATE 12 22*4882a593Smuzhiyun #define IMX6SL_CLK_USBPHY2_GATE 13 23*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_POST_DIV 14 24*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_POST_DIV 15 25*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5_VIDEO_DIV 16 26*4882a593Smuzhiyun #define IMX6SL_CLK_ENET_REF 17 27*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD0 18 28*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD1 19 29*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_PFD2 20 30*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD0 21 31*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD1 22 32*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD2 23 33*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_PFD3 24 34*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2_198M 25 35*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_120M 26 36*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_80M 27 37*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3_60M 28 38*4882a593Smuzhiyun #define IMX6SL_CLK_STEP 29 39*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1_SW 30 40*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_ALT_SEL 31 41*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_SEL 32 42*4882a593Smuzhiyun #define IMX6SL_CLK_PRE_PERIPH2_SEL 33 43*4882a593Smuzhiyun #define IMX6SL_CLK_PRE_PERIPH_SEL 34 44*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 45*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH_CLK2_SEL 36 46*4882a593Smuzhiyun #define IMX6SL_CLK_CSI_SEL 37 47*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI_SEL 38 48*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1_SEL 39 49*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2_SEL 40 50*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3_SEL 41 51*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4_SEL 42 52*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_SEL 43 53*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_SEL 44 54*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_SEL 45 55*4882a593Smuzhiyun #define IMX6SL_CLK_PERCLK_SEL 46 56*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI_SEL 47 57*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI_SEL 48 58*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG_SEL 49 59*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_SEL 50 60*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_SEL 51 61*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_SEL 52 62*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_SEL 53 63*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_SEL 54 64*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 65*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI_SEL 56 66*4882a593Smuzhiyun #define IMX6SL_CLK_UART_SEL 57 67*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH 58 68*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2 59 69*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM_PODF 60 70*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH_CLK2_PODF 61 71*4882a593Smuzhiyun #define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 72*4882a593Smuzhiyun #define IMX6SL_CLK_IPG 63 73*4882a593Smuzhiyun #define IMX6SL_CLK_CSI_PODF 64 74*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI_PODF 65 75*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1_PODF 66 76*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2_PODF 67 77*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3_PODF 68 78*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4_PODF 69 79*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_PRED 70 80*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_PODF 71 81*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_PRED 72 82*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_PODF 73 83*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_PRED 74 84*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_PODF 75 85*4882a593Smuzhiyun #define IMX6SL_CLK_PERCLK 76 86*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI_PODF 77 87*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI_PODF 78 88*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG_PODF 79 89*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_PODF 80 90*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_PRED 81 91*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_PRED 82 92*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX_PODF 83 93*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX_PODF 84 94*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_PRED 85 95*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF0_PODF 86 96*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_PRED 87 97*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF1_PODF 88 98*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 99*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 100*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI_ROOT 91 101*4882a593Smuzhiyun #define IMX6SL_CLK_UART_ROOT 92 102*4882a593Smuzhiyun #define IMX6SL_CLK_AHB 93 103*4882a593Smuzhiyun #define IMX6SL_CLK_MMDC_ROOT 94 104*4882a593Smuzhiyun #define IMX6SL_CLK_ARM 95 105*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI1 96 106*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI2 97 107*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI3 98 108*4882a593Smuzhiyun #define IMX6SL_CLK_ECSPI4 99 109*4882a593Smuzhiyun #define IMX6SL_CLK_EPIT1 100 110*4882a593Smuzhiyun #define IMX6SL_CLK_EPIT2 101 111*4882a593Smuzhiyun #define IMX6SL_CLK_EXTERN_AUDIO 102 112*4882a593Smuzhiyun #define IMX6SL_CLK_GPT 103 113*4882a593Smuzhiyun #define IMX6SL_CLK_GPT_SERIAL 104 114*4882a593Smuzhiyun #define IMX6SL_CLK_GPU2D_OVG 105 115*4882a593Smuzhiyun #define IMX6SL_CLK_I2C1 106 116*4882a593Smuzhiyun #define IMX6SL_CLK_I2C2 107 117*4882a593Smuzhiyun #define IMX6SL_CLK_I2C3 108 118*4882a593Smuzhiyun #define IMX6SL_CLK_OCOTP 109 119*4882a593Smuzhiyun #define IMX6SL_CLK_CSI 110 120*4882a593Smuzhiyun #define IMX6SL_CLK_PXP_AXI 111 121*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_AXI 112 122*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_AXI 113 123*4882a593Smuzhiyun #define IMX6SL_CLK_LCDIF_PIX 114 124*4882a593Smuzhiyun #define IMX6SL_CLK_EPDC_PIX 115 125*4882a593Smuzhiyun #define IMX6SL_CLK_OCRAM 116 126*4882a593Smuzhiyun #define IMX6SL_CLK_PWM1 117 127*4882a593Smuzhiyun #define IMX6SL_CLK_PWM2 118 128*4882a593Smuzhiyun #define IMX6SL_CLK_PWM3 119 129*4882a593Smuzhiyun #define IMX6SL_CLK_PWM4 120 130*4882a593Smuzhiyun #define IMX6SL_CLK_SDMA 121 131*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF 122 132*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1 123 133*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2 124 134*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3 125 135*4882a593Smuzhiyun #define IMX6SL_CLK_UART 126 136*4882a593Smuzhiyun #define IMX6SL_CLK_UART_SERIAL 127 137*4882a593Smuzhiyun #define IMX6SL_CLK_USBOH3 128 138*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC1 129 139*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC2 130 140*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC3 131 141*4882a593Smuzhiyun #define IMX6SL_CLK_USDHC4 132 142*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 143*4882a593Smuzhiyun #define IMX6SL_CLK_SPBA 134 144*4882a593Smuzhiyun #define IMX6SL_CLK_ENET 135 145*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_SEL 136 146*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_OUT 137 147*4882a593Smuzhiyun #define IMX6SL_CLK_LVDS1_IN 138 148*4882a593Smuzhiyun #define IMX6SL_CLK_ANACLK1 139 149*4882a593Smuzhiyun #define IMX6SL_PLL1_BYPASS_SRC 140 150*4882a593Smuzhiyun #define IMX6SL_PLL2_BYPASS_SRC 141 151*4882a593Smuzhiyun #define IMX6SL_PLL3_BYPASS_SRC 142 152*4882a593Smuzhiyun #define IMX6SL_PLL4_BYPASS_SRC 143 153*4882a593Smuzhiyun #define IMX6SL_PLL5_BYPASS_SRC 144 154*4882a593Smuzhiyun #define IMX6SL_PLL6_BYPASS_SRC 145 155*4882a593Smuzhiyun #define IMX6SL_PLL7_BYPASS_SRC 146 156*4882a593Smuzhiyun #define IMX6SL_CLK_PLL1 147 157*4882a593Smuzhiyun #define IMX6SL_CLK_PLL2 148 158*4882a593Smuzhiyun #define IMX6SL_CLK_PLL3 149 159*4882a593Smuzhiyun #define IMX6SL_CLK_PLL4 150 160*4882a593Smuzhiyun #define IMX6SL_CLK_PLL5 151 161*4882a593Smuzhiyun #define IMX6SL_CLK_PLL6 152 162*4882a593Smuzhiyun #define IMX6SL_CLK_PLL7 153 163*4882a593Smuzhiyun #define IMX6SL_PLL1_BYPASS 154 164*4882a593Smuzhiyun #define IMX6SL_PLL2_BYPASS 155 165*4882a593Smuzhiyun #define IMX6SL_PLL3_BYPASS 156 166*4882a593Smuzhiyun #define IMX6SL_PLL4_BYPASS 157 167*4882a593Smuzhiyun #define IMX6SL_PLL5_BYPASS 158 168*4882a593Smuzhiyun #define IMX6SL_PLL6_BYPASS 159 169*4882a593Smuzhiyun #define IMX6SL_PLL7_BYPASS 160 170*4882a593Smuzhiyun #define IMX6SL_CLK_SSI1_IPG 161 171*4882a593Smuzhiyun #define IMX6SL_CLK_SSI2_IPG 162 172*4882a593Smuzhiyun #define IMX6SL_CLK_SSI3_IPG 163 173*4882a593Smuzhiyun #define IMX6SL_CLK_SPDIF_GCLK 164 174*4882a593Smuzhiyun #define IMX6SL_CLK_MMDC_P0_IPG 165 175*4882a593Smuzhiyun #define IMX6SL_CLK_MMDC_P1_IPG 166 176*4882a593Smuzhiyun #define IMX6SL_CLK_END 167 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ 179