1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX5_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX5_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX5_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX5_CLK_CKIL 1 11*4882a593Smuzhiyun #define IMX5_CLK_OSC 2 12*4882a593Smuzhiyun #define IMX5_CLK_CKIH1 3 13*4882a593Smuzhiyun #define IMX5_CLK_CKIH2 4 14*4882a593Smuzhiyun #define IMX5_CLK_AHB 5 15*4882a593Smuzhiyun #define IMX5_CLK_IPG 6 16*4882a593Smuzhiyun #define IMX5_CLK_AXI_A 7 17*4882a593Smuzhiyun #define IMX5_CLK_AXI_B 8 18*4882a593Smuzhiyun #define IMX5_CLK_UART_PRED 9 19*4882a593Smuzhiyun #define IMX5_CLK_UART_ROOT 10 20*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_A_PRED 11 21*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_B_PRED 12 22*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_C_SEL 13 23*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_D_SEL 14 24*4882a593Smuzhiyun #define IMX5_CLK_EMI_SEL 15 25*4882a593Smuzhiyun #define IMX5_CLK_EMI_SLOW_PODF 16 26*4882a593Smuzhiyun #define IMX5_CLK_NFC_PODF 17 27*4882a593Smuzhiyun #define IMX5_CLK_ECSPI_PRED 18 28*4882a593Smuzhiyun #define IMX5_CLK_ECSPI_PODF 19 29*4882a593Smuzhiyun #define IMX5_CLK_USBOH3_PRED 20 30*4882a593Smuzhiyun #define IMX5_CLK_USBOH3_PODF 21 31*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY_PRED 22 32*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY_PODF 23 33*4882a593Smuzhiyun #define IMX5_CLK_CPU_PODF 24 34*4882a593Smuzhiyun #define IMX5_CLK_DI_PRED 25 35*4882a593Smuzhiyun #define IMX5_CLK_TVE_SEL 27 36*4882a593Smuzhiyun #define IMX5_CLK_UART1_IPG_GATE 28 37*4882a593Smuzhiyun #define IMX5_CLK_UART1_PER_GATE 29 38*4882a593Smuzhiyun #define IMX5_CLK_UART2_IPG_GATE 30 39*4882a593Smuzhiyun #define IMX5_CLK_UART2_PER_GATE 31 40*4882a593Smuzhiyun #define IMX5_CLK_UART3_IPG_GATE 32 41*4882a593Smuzhiyun #define IMX5_CLK_UART3_PER_GATE 33 42*4882a593Smuzhiyun #define IMX5_CLK_I2C1_GATE 34 43*4882a593Smuzhiyun #define IMX5_CLK_I2C2_GATE 35 44*4882a593Smuzhiyun #define IMX5_CLK_GPT_IPG_GATE 36 45*4882a593Smuzhiyun #define IMX5_CLK_PWM1_IPG_GATE 37 46*4882a593Smuzhiyun #define IMX5_CLK_PWM1_HF_GATE 38 47*4882a593Smuzhiyun #define IMX5_CLK_PWM2_IPG_GATE 39 48*4882a593Smuzhiyun #define IMX5_CLK_PWM2_HF_GATE 40 49*4882a593Smuzhiyun #define IMX5_CLK_GPT_HF_GATE 41 50*4882a593Smuzhiyun #define IMX5_CLK_FEC_GATE 42 51*4882a593Smuzhiyun #define IMX5_CLK_USBOH3_PER_GATE 43 52*4882a593Smuzhiyun #define IMX5_CLK_ESDHC1_IPG_GATE 44 53*4882a593Smuzhiyun #define IMX5_CLK_ESDHC2_IPG_GATE 45 54*4882a593Smuzhiyun #define IMX5_CLK_ESDHC3_IPG_GATE 46 55*4882a593Smuzhiyun #define IMX5_CLK_ESDHC4_IPG_GATE 47 56*4882a593Smuzhiyun #define IMX5_CLK_SSI1_IPG_GATE 48 57*4882a593Smuzhiyun #define IMX5_CLK_SSI2_IPG_GATE 49 58*4882a593Smuzhiyun #define IMX5_CLK_SSI3_IPG_GATE 50 59*4882a593Smuzhiyun #define IMX5_CLK_ECSPI1_IPG_GATE 51 60*4882a593Smuzhiyun #define IMX5_CLK_ECSPI1_PER_GATE 52 61*4882a593Smuzhiyun #define IMX5_CLK_ECSPI2_IPG_GATE 53 62*4882a593Smuzhiyun #define IMX5_CLK_ECSPI2_PER_GATE 54 63*4882a593Smuzhiyun #define IMX5_CLK_CSPI_IPG_GATE 55 64*4882a593Smuzhiyun #define IMX5_CLK_SDMA_GATE 56 65*4882a593Smuzhiyun #define IMX5_CLK_EMI_SLOW_GATE 57 66*4882a593Smuzhiyun #define IMX5_CLK_IPU_SEL 58 67*4882a593Smuzhiyun #define IMX5_CLK_IPU_GATE 59 68*4882a593Smuzhiyun #define IMX5_CLK_NFC_GATE 60 69*4882a593Smuzhiyun #define IMX5_CLK_IPU_DI1_GATE 61 70*4882a593Smuzhiyun #define IMX5_CLK_VPU_SEL 62 71*4882a593Smuzhiyun #define IMX5_CLK_VPU_GATE 63 72*4882a593Smuzhiyun #define IMX5_CLK_VPU_REFERENCE_GATE 64 73*4882a593Smuzhiyun #define IMX5_CLK_UART4_IPG_GATE 65 74*4882a593Smuzhiyun #define IMX5_CLK_UART4_PER_GATE 66 75*4882a593Smuzhiyun #define IMX5_CLK_UART5_IPG_GATE 67 76*4882a593Smuzhiyun #define IMX5_CLK_UART5_PER_GATE 68 77*4882a593Smuzhiyun #define IMX5_CLK_TVE_GATE 69 78*4882a593Smuzhiyun #define IMX5_CLK_TVE_PRED 70 79*4882a593Smuzhiyun #define IMX5_CLK_ESDHC1_PER_GATE 71 80*4882a593Smuzhiyun #define IMX5_CLK_ESDHC2_PER_GATE 72 81*4882a593Smuzhiyun #define IMX5_CLK_ESDHC3_PER_GATE 73 82*4882a593Smuzhiyun #define IMX5_CLK_ESDHC4_PER_GATE 74 83*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY_GATE 75 84*4882a593Smuzhiyun #define IMX5_CLK_HSI2C_GATE 76 85*4882a593Smuzhiyun #define IMX5_CLK_MIPI_HSC1_GATE 77 86*4882a593Smuzhiyun #define IMX5_CLK_MIPI_HSC2_GATE 78 87*4882a593Smuzhiyun #define IMX5_CLK_MIPI_ESC_GATE 79 88*4882a593Smuzhiyun #define IMX5_CLK_MIPI_HSP_GATE 80 89*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI1_DIV_3_5 81 90*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI1_DIV 82 91*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI0_DIV_3_5 83 92*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI0_DIV 84 93*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI1_GATE 85 94*4882a593Smuzhiyun #define IMX5_CLK_CAN2_SERIAL_GATE 86 95*4882a593Smuzhiyun #define IMX5_CLK_CAN2_IPG_GATE 87 96*4882a593Smuzhiyun #define IMX5_CLK_I2C3_GATE 88 97*4882a593Smuzhiyun #define IMX5_CLK_LP_APM 89 98*4882a593Smuzhiyun #define IMX5_CLK_PERIPH_APM 90 99*4882a593Smuzhiyun #define IMX5_CLK_MAIN_BUS 91 100*4882a593Smuzhiyun #define IMX5_CLK_AHB_MAX 92 101*4882a593Smuzhiyun #define IMX5_CLK_AIPS_TZ1 93 102*4882a593Smuzhiyun #define IMX5_CLK_AIPS_TZ2 94 103*4882a593Smuzhiyun #define IMX5_CLK_TMAX1 95 104*4882a593Smuzhiyun #define IMX5_CLK_TMAX2 96 105*4882a593Smuzhiyun #define IMX5_CLK_TMAX3 97 106*4882a593Smuzhiyun #define IMX5_CLK_SPBA 98 107*4882a593Smuzhiyun #define IMX5_CLK_UART_SEL 99 108*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_A_SEL 100 109*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_B_SEL 101 110*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_A_PODF 102 111*4882a593Smuzhiyun #define IMX5_CLK_ESDHC_B_PODF 103 112*4882a593Smuzhiyun #define IMX5_CLK_ECSPI_SEL 104 113*4882a593Smuzhiyun #define IMX5_CLK_USBOH3_SEL 105 114*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY_SEL 106 115*4882a593Smuzhiyun #define IMX5_CLK_IIM_GATE 107 116*4882a593Smuzhiyun #define IMX5_CLK_USBOH3_GATE 108 117*4882a593Smuzhiyun #define IMX5_CLK_EMI_FAST_GATE 109 118*4882a593Smuzhiyun #define IMX5_CLK_IPU_DI0_GATE 110 119*4882a593Smuzhiyun #define IMX5_CLK_GPC_DVFS 111 120*4882a593Smuzhiyun #define IMX5_CLK_PLL1_SW 112 121*4882a593Smuzhiyun #define IMX5_CLK_PLL2_SW 113 122*4882a593Smuzhiyun #define IMX5_CLK_PLL3_SW 114 123*4882a593Smuzhiyun #define IMX5_CLK_IPU_DI0_SEL 115 124*4882a593Smuzhiyun #define IMX5_CLK_IPU_DI1_SEL 116 125*4882a593Smuzhiyun #define IMX5_CLK_TVE_EXT_SEL 117 126*4882a593Smuzhiyun #define IMX5_CLK_MX51_MIPI 118 127*4882a593Smuzhiyun #define IMX5_CLK_PLL4_SW 119 128*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI1_SEL 120 129*4882a593Smuzhiyun #define IMX5_CLK_DI_PLL4_PODF 121 130*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI0_SEL 122 131*4882a593Smuzhiyun #define IMX5_CLK_LDB_DI0_GATE 123 132*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY1_GATE 124 133*4882a593Smuzhiyun #define IMX5_CLK_USB_PHY2_GATE 125 134*4882a593Smuzhiyun #define IMX5_CLK_PER_LP_APM 126 135*4882a593Smuzhiyun #define IMX5_CLK_PER_PRED1 127 136*4882a593Smuzhiyun #define IMX5_CLK_PER_PRED2 128 137*4882a593Smuzhiyun #define IMX5_CLK_PER_PODF 129 138*4882a593Smuzhiyun #define IMX5_CLK_PER_ROOT 130 139*4882a593Smuzhiyun #define IMX5_CLK_SSI_APM 131 140*4882a593Smuzhiyun #define IMX5_CLK_SSI1_ROOT_SEL 132 141*4882a593Smuzhiyun #define IMX5_CLK_SSI2_ROOT_SEL 133 142*4882a593Smuzhiyun #define IMX5_CLK_SSI3_ROOT_SEL 134 143*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT1_SEL 135 144*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT2_SEL 136 145*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT1_COM_SEL 137 146*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT2_COM_SEL 138 147*4882a593Smuzhiyun #define IMX5_CLK_SSI1_ROOT_PRED 139 148*4882a593Smuzhiyun #define IMX5_CLK_SSI1_ROOT_PODF 140 149*4882a593Smuzhiyun #define IMX5_CLK_SSI2_ROOT_PRED 141 150*4882a593Smuzhiyun #define IMX5_CLK_SSI2_ROOT_PODF 142 151*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT1_PRED 143 152*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT1_PODF 144 153*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT2_PRED 145 154*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT2_PODF 146 155*4882a593Smuzhiyun #define IMX5_CLK_SSI1_ROOT_GATE 147 156*4882a593Smuzhiyun #define IMX5_CLK_SSI2_ROOT_GATE 148 157*4882a593Smuzhiyun #define IMX5_CLK_SSI3_ROOT_GATE 149 158*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT1_GATE 150 159*4882a593Smuzhiyun #define IMX5_CLK_SSI_EXT2_GATE 151 160*4882a593Smuzhiyun #define IMX5_CLK_EPIT1_IPG_GATE 152 161*4882a593Smuzhiyun #define IMX5_CLK_EPIT1_HF_GATE 153 162*4882a593Smuzhiyun #define IMX5_CLK_EPIT2_IPG_GATE 154 163*4882a593Smuzhiyun #define IMX5_CLK_EPIT2_HF_GATE 155 164*4882a593Smuzhiyun #define IMX5_CLK_CAN_SEL 156 165*4882a593Smuzhiyun #define IMX5_CLK_CAN1_SERIAL_GATE 157 166*4882a593Smuzhiyun #define IMX5_CLK_CAN1_IPG_GATE 158 167*4882a593Smuzhiyun #define IMX5_CLK_OWIRE_GATE 159 168*4882a593Smuzhiyun #define IMX5_CLK_GPU3D_SEL 160 169*4882a593Smuzhiyun #define IMX5_CLK_GPU2D_SEL 161 170*4882a593Smuzhiyun #define IMX5_CLK_GPU3D_GATE 162 171*4882a593Smuzhiyun #define IMX5_CLK_GPU2D_GATE 163 172*4882a593Smuzhiyun #define IMX5_CLK_GARB_GATE 164 173*4882a593Smuzhiyun #define IMX5_CLK_CKO1_SEL 165 174*4882a593Smuzhiyun #define IMX5_CLK_CKO1_PODF 166 175*4882a593Smuzhiyun #define IMX5_CLK_CKO1 167 176*4882a593Smuzhiyun #define IMX5_CLK_CKO2_SEL 168 177*4882a593Smuzhiyun #define IMX5_CLK_CKO2_PODF 169 178*4882a593Smuzhiyun #define IMX5_CLK_CKO2 170 179*4882a593Smuzhiyun #define IMX5_CLK_SRTC_GATE 171 180*4882a593Smuzhiyun #define IMX5_CLK_PATA_GATE 172 181*4882a593Smuzhiyun #define IMX5_CLK_SATA_GATE 173 182*4882a593Smuzhiyun #define IMX5_CLK_SPDIF_XTAL_SEL 174 183*4882a593Smuzhiyun #define IMX5_CLK_SPDIF0_SEL 175 184*4882a593Smuzhiyun #define IMX5_CLK_SPDIF1_SEL 176 185*4882a593Smuzhiyun #define IMX5_CLK_SPDIF0_PRED 177 186*4882a593Smuzhiyun #define IMX5_CLK_SPDIF0_PODF 178 187*4882a593Smuzhiyun #define IMX5_CLK_SPDIF1_PRED 179 188*4882a593Smuzhiyun #define IMX5_CLK_SPDIF1_PODF 180 189*4882a593Smuzhiyun #define IMX5_CLK_SPDIF0_COM_SEL 181 190*4882a593Smuzhiyun #define IMX5_CLK_SPDIF1_COM_SEL 182 191*4882a593Smuzhiyun #define IMX5_CLK_SPDIF0_GATE 183 192*4882a593Smuzhiyun #define IMX5_CLK_SPDIF1_GATE 184 193*4882a593Smuzhiyun #define IMX5_CLK_SPDIF_IPG_GATE 185 194*4882a593Smuzhiyun #define IMX5_CLK_OCRAM 186 195*4882a593Smuzhiyun #define IMX5_CLK_SAHARA_IPG_GATE 187 196*4882a593Smuzhiyun #define IMX5_CLK_SATA_REF 188 197*4882a593Smuzhiyun #define IMX5_CLK_STEP_SEL 189 198*4882a593Smuzhiyun #define IMX5_CLK_CPU_PODF_SEL 190 199*4882a593Smuzhiyun #define IMX5_CLK_ARM 191 200*4882a593Smuzhiyun #define IMX5_CLK_FIRI_PRED 192 201*4882a593Smuzhiyun #define IMX5_CLK_FIRI_SEL 193 202*4882a593Smuzhiyun #define IMX5_CLK_FIRI_PODF 194 203*4882a593Smuzhiyun #define IMX5_CLK_FIRI_SERIAL_GATE 195 204*4882a593Smuzhiyun #define IMX5_CLK_FIRI_IPG_GATE 196 205*4882a593Smuzhiyun #define IMX5_CLK_CSI0_MCLK1_PRED 197 206*4882a593Smuzhiyun #define IMX5_CLK_CSI0_MCLK1_SEL 198 207*4882a593Smuzhiyun #define IMX5_CLK_CSI0_MCLK1_PODF 199 208*4882a593Smuzhiyun #define IMX5_CLK_CSI0_MCLK1_GATE 200 209*4882a593Smuzhiyun #define IMX5_CLK_IEEE1588_PRED 201 210*4882a593Smuzhiyun #define IMX5_CLK_IEEE1588_SEL 202 211*4882a593Smuzhiyun #define IMX5_CLK_IEEE1588_PODF 203 212*4882a593Smuzhiyun #define IMX5_CLK_IEEE1588_GATE 204 213*4882a593Smuzhiyun #define IMX5_CLK_SCC2_IPG_GATE 205 214*4882a593Smuzhiyun #define IMX5_CLK_END 206 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 217