1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX27_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX27_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX27_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX27_CLK_CKIH 1 11*4882a593Smuzhiyun #define IMX27_CLK_CKIL 2 12*4882a593Smuzhiyun #define IMX27_CLK_MPLL 3 13*4882a593Smuzhiyun #define IMX27_CLK_SPLL 4 14*4882a593Smuzhiyun #define IMX27_CLK_MPLL_MAIN2 5 15*4882a593Smuzhiyun #define IMX27_CLK_AHB 6 16*4882a593Smuzhiyun #define IMX27_CLK_IPG 7 17*4882a593Smuzhiyun #define IMX27_CLK_NFC_DIV 8 18*4882a593Smuzhiyun #define IMX27_CLK_PER1_DIV 9 19*4882a593Smuzhiyun #define IMX27_CLK_PER2_DIV 10 20*4882a593Smuzhiyun #define IMX27_CLK_PER3_DIV 11 21*4882a593Smuzhiyun #define IMX27_CLK_PER4_DIV 12 22*4882a593Smuzhiyun #define IMX27_CLK_VPU_SEL 13 23*4882a593Smuzhiyun #define IMX27_CLK_VPU_DIV 14 24*4882a593Smuzhiyun #define IMX27_CLK_USB_DIV 15 25*4882a593Smuzhiyun #define IMX27_CLK_CPU_SEL 16 26*4882a593Smuzhiyun #define IMX27_CLK_CLKO_SEL 17 27*4882a593Smuzhiyun #define IMX27_CLK_CPU_DIV 18 28*4882a593Smuzhiyun #define IMX27_CLK_CLKO_DIV 19 29*4882a593Smuzhiyun #define IMX27_CLK_SSI1_SEL 20 30*4882a593Smuzhiyun #define IMX27_CLK_SSI2_SEL 21 31*4882a593Smuzhiyun #define IMX27_CLK_SSI1_DIV 22 32*4882a593Smuzhiyun #define IMX27_CLK_SSI2_DIV 23 33*4882a593Smuzhiyun #define IMX27_CLK_CLKO_EN 24 34*4882a593Smuzhiyun #define IMX27_CLK_SSI2_IPG_GATE 25 35*4882a593Smuzhiyun #define IMX27_CLK_SSI1_IPG_GATE 26 36*4882a593Smuzhiyun #define IMX27_CLK_SLCDC_IPG_GATE 27 37*4882a593Smuzhiyun #define IMX27_CLK_SDHC3_IPG_GATE 28 38*4882a593Smuzhiyun #define IMX27_CLK_SDHC2_IPG_GATE 29 39*4882a593Smuzhiyun #define IMX27_CLK_SDHC1_IPG_GATE 30 40*4882a593Smuzhiyun #define IMX27_CLK_SCC_IPG_GATE 31 41*4882a593Smuzhiyun #define IMX27_CLK_SAHARA_IPG_GATE 32 42*4882a593Smuzhiyun #define IMX27_CLK_RTC_IPG_GATE 33 43*4882a593Smuzhiyun #define IMX27_CLK_PWM_IPG_GATE 34 44*4882a593Smuzhiyun #define IMX27_CLK_OWIRE_IPG_GATE 35 45*4882a593Smuzhiyun #define IMX27_CLK_LCDC_IPG_GATE 36 46*4882a593Smuzhiyun #define IMX27_CLK_KPP_IPG_GATE 37 47*4882a593Smuzhiyun #define IMX27_CLK_IIM_IPG_GATE 38 48*4882a593Smuzhiyun #define IMX27_CLK_I2C2_IPG_GATE 39 49*4882a593Smuzhiyun #define IMX27_CLK_I2C1_IPG_GATE 40 50*4882a593Smuzhiyun #define IMX27_CLK_GPT6_IPG_GATE 41 51*4882a593Smuzhiyun #define IMX27_CLK_GPT5_IPG_GATE 42 52*4882a593Smuzhiyun #define IMX27_CLK_GPT4_IPG_GATE 43 53*4882a593Smuzhiyun #define IMX27_CLK_GPT3_IPG_GATE 44 54*4882a593Smuzhiyun #define IMX27_CLK_GPT2_IPG_GATE 45 55*4882a593Smuzhiyun #define IMX27_CLK_GPT1_IPG_GATE 46 56*4882a593Smuzhiyun #define IMX27_CLK_GPIO_IPG_GATE 47 57*4882a593Smuzhiyun #define IMX27_CLK_FEC_IPG_GATE 48 58*4882a593Smuzhiyun #define IMX27_CLK_EMMA_IPG_GATE 49 59*4882a593Smuzhiyun #define IMX27_CLK_DMA_IPG_GATE 50 60*4882a593Smuzhiyun #define IMX27_CLK_CSPI3_IPG_GATE 51 61*4882a593Smuzhiyun #define IMX27_CLK_CSPI2_IPG_GATE 52 62*4882a593Smuzhiyun #define IMX27_CLK_CSPI1_IPG_GATE 53 63*4882a593Smuzhiyun #define IMX27_CLK_NFC_BAUD_GATE 54 64*4882a593Smuzhiyun #define IMX27_CLK_SSI2_BAUD_GATE 55 65*4882a593Smuzhiyun #define IMX27_CLK_SSI1_BAUD_GATE 56 66*4882a593Smuzhiyun #define IMX27_CLK_VPU_BAUD_GATE 57 67*4882a593Smuzhiyun #define IMX27_CLK_PER4_GATE 58 68*4882a593Smuzhiyun #define IMX27_CLK_PER3_GATE 59 69*4882a593Smuzhiyun #define IMX27_CLK_PER2_GATE 60 70*4882a593Smuzhiyun #define IMX27_CLK_PER1_GATE 61 71*4882a593Smuzhiyun #define IMX27_CLK_USB_AHB_GATE 62 72*4882a593Smuzhiyun #define IMX27_CLK_SLCDC_AHB_GATE 63 73*4882a593Smuzhiyun #define IMX27_CLK_SAHARA_AHB_GATE 64 74*4882a593Smuzhiyun #define IMX27_CLK_LCDC_AHB_GATE 65 75*4882a593Smuzhiyun #define IMX27_CLK_VPU_AHB_GATE 66 76*4882a593Smuzhiyun #define IMX27_CLK_FEC_AHB_GATE 67 77*4882a593Smuzhiyun #define IMX27_CLK_EMMA_AHB_GATE 68 78*4882a593Smuzhiyun #define IMX27_CLK_EMI_AHB_GATE 69 79*4882a593Smuzhiyun #define IMX27_CLK_DMA_AHB_GATE 70 80*4882a593Smuzhiyun #define IMX27_CLK_CSI_AHB_GATE 71 81*4882a593Smuzhiyun #define IMX27_CLK_BROM_AHB_GATE 72 82*4882a593Smuzhiyun #define IMX27_CLK_ATA_AHB_GATE 73 83*4882a593Smuzhiyun #define IMX27_CLK_WDOG_IPG_GATE 74 84*4882a593Smuzhiyun #define IMX27_CLK_USB_IPG_GATE 75 85*4882a593Smuzhiyun #define IMX27_CLK_UART6_IPG_GATE 76 86*4882a593Smuzhiyun #define IMX27_CLK_UART5_IPG_GATE 77 87*4882a593Smuzhiyun #define IMX27_CLK_UART4_IPG_GATE 78 88*4882a593Smuzhiyun #define IMX27_CLK_UART3_IPG_GATE 79 89*4882a593Smuzhiyun #define IMX27_CLK_UART2_IPG_GATE 80 90*4882a593Smuzhiyun #define IMX27_CLK_UART1_IPG_GATE 81 91*4882a593Smuzhiyun #define IMX27_CLK_CKIH_DIV1P5 82 92*4882a593Smuzhiyun #define IMX27_CLK_FPM 83 93*4882a593Smuzhiyun #define IMX27_CLK_MPLL_OSC_SEL 84 94*4882a593Smuzhiyun #define IMX27_CLK_MPLL_SEL 85 95*4882a593Smuzhiyun #define IMX27_CLK_SPLL_GATE 86 96*4882a593Smuzhiyun #define IMX27_CLK_MSHC_DIV 87 97*4882a593Smuzhiyun #define IMX27_CLK_RTIC_IPG_GATE 88 98*4882a593Smuzhiyun #define IMX27_CLK_MSHC_IPG_GATE 89 99*4882a593Smuzhiyun #define IMX27_CLK_RTIC_AHB_GATE 90 100*4882a593Smuzhiyun #define IMX27_CLK_MSHC_BAUD_GATE 91 101*4882a593Smuzhiyun #define IMX27_CLK_CKIH_GATE 92 102*4882a593Smuzhiyun #define IMX27_CLK_MAX 93 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif 105