1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX21_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX21_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX21_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX21_CLK_CKIL 1 11*4882a593Smuzhiyun #define IMX21_CLK_CKIH 2 12*4882a593Smuzhiyun #define IMX21_CLK_FPM 3 13*4882a593Smuzhiyun #define IMX21_CLK_CKIH_DIV1P5 4 14*4882a593Smuzhiyun #define IMX21_CLK_MPLL_GATE 5 15*4882a593Smuzhiyun #define IMX21_CLK_SPLL_GATE 6 16*4882a593Smuzhiyun #define IMX21_CLK_FPM_GATE 7 17*4882a593Smuzhiyun #define IMX21_CLK_CKIH_GATE 8 18*4882a593Smuzhiyun #define IMX21_CLK_MPLL_OSC_SEL 9 19*4882a593Smuzhiyun #define IMX21_CLK_IPG 10 20*4882a593Smuzhiyun #define IMX21_CLK_HCLK 11 21*4882a593Smuzhiyun #define IMX21_CLK_MPLL_SEL 12 22*4882a593Smuzhiyun #define IMX21_CLK_SPLL_SEL 13 23*4882a593Smuzhiyun #define IMX21_CLK_SSI1_SEL 14 24*4882a593Smuzhiyun #define IMX21_CLK_SSI2_SEL 15 25*4882a593Smuzhiyun #define IMX21_CLK_USB_DIV 16 26*4882a593Smuzhiyun #define IMX21_CLK_FCLK 17 27*4882a593Smuzhiyun #define IMX21_CLK_MPLL 18 28*4882a593Smuzhiyun #define IMX21_CLK_SPLL 19 29*4882a593Smuzhiyun #define IMX21_CLK_NFC_DIV 20 30*4882a593Smuzhiyun #define IMX21_CLK_SSI1_DIV 21 31*4882a593Smuzhiyun #define IMX21_CLK_SSI2_DIV 22 32*4882a593Smuzhiyun #define IMX21_CLK_PER1 23 33*4882a593Smuzhiyun #define IMX21_CLK_PER2 24 34*4882a593Smuzhiyun #define IMX21_CLK_PER3 25 35*4882a593Smuzhiyun #define IMX21_CLK_PER4 26 36*4882a593Smuzhiyun #define IMX21_CLK_UART1_IPG_GATE 27 37*4882a593Smuzhiyun #define IMX21_CLK_UART2_IPG_GATE 28 38*4882a593Smuzhiyun #define IMX21_CLK_UART3_IPG_GATE 29 39*4882a593Smuzhiyun #define IMX21_CLK_UART4_IPG_GATE 30 40*4882a593Smuzhiyun #define IMX21_CLK_CSPI1_IPG_GATE 31 41*4882a593Smuzhiyun #define IMX21_CLK_CSPI2_IPG_GATE 32 42*4882a593Smuzhiyun #define IMX21_CLK_SSI1_GATE 33 43*4882a593Smuzhiyun #define IMX21_CLK_SSI2_GATE 34 44*4882a593Smuzhiyun #define IMX21_CLK_SDHC1_IPG_GATE 35 45*4882a593Smuzhiyun #define IMX21_CLK_SDHC2_IPG_GATE 36 46*4882a593Smuzhiyun #define IMX21_CLK_GPIO_GATE 37 47*4882a593Smuzhiyun #define IMX21_CLK_I2C_GATE 38 48*4882a593Smuzhiyun #define IMX21_CLK_DMA_GATE 39 49*4882a593Smuzhiyun #define IMX21_CLK_USB_GATE 40 50*4882a593Smuzhiyun #define IMX21_CLK_EMMA_GATE 41 51*4882a593Smuzhiyun #define IMX21_CLK_SSI2_BAUD_GATE 42 52*4882a593Smuzhiyun #define IMX21_CLK_SSI1_BAUD_GATE 43 53*4882a593Smuzhiyun #define IMX21_CLK_LCDC_IPG_GATE 44 54*4882a593Smuzhiyun #define IMX21_CLK_NFC_GATE 45 55*4882a593Smuzhiyun #define IMX21_CLK_LCDC_HCLK_GATE 46 56*4882a593Smuzhiyun #define IMX21_CLK_PER4_GATE 47 57*4882a593Smuzhiyun #define IMX21_CLK_BMI_GATE 48 58*4882a593Smuzhiyun #define IMX21_CLK_USB_HCLK_GATE 49 59*4882a593Smuzhiyun #define IMX21_CLK_SLCDC_GATE 50 60*4882a593Smuzhiyun #define IMX21_CLK_SLCDC_HCLK_GATE 51 61*4882a593Smuzhiyun #define IMX21_CLK_EMMA_HCLK_GATE 52 62*4882a593Smuzhiyun #define IMX21_CLK_BROM_GATE 53 63*4882a593Smuzhiyun #define IMX21_CLK_DMA_HCLK_GATE 54 64*4882a593Smuzhiyun #define IMX21_CLK_CSI_HCLK_GATE 55 65*4882a593Smuzhiyun #define IMX21_CLK_CSPI3_IPG_GATE 56 66*4882a593Smuzhiyun #define IMX21_CLK_WDOG_GATE 57 67*4882a593Smuzhiyun #define IMX21_CLK_GPT1_IPG_GATE 58 68*4882a593Smuzhiyun #define IMX21_CLK_GPT2_IPG_GATE 59 69*4882a593Smuzhiyun #define IMX21_CLK_GPT3_IPG_GATE 60 70*4882a593Smuzhiyun #define IMX21_CLK_PWM_IPG_GATE 61 71*4882a593Smuzhiyun #define IMX21_CLK_RTC_GATE 62 72*4882a593Smuzhiyun #define IMX21_CLK_KPP_GATE 63 73*4882a593Smuzhiyun #define IMX21_CLK_OWIRE_GATE 64 74*4882a593Smuzhiyun #define IMX21_CLK_MAX 65 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77