1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX1_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX1_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX1_CLK_DUMMY 0 10*4882a593Smuzhiyun #define IMX1_CLK_CLK32 1 11*4882a593Smuzhiyun #define IMX1_CLK_CLK16M_EXT 2 12*4882a593Smuzhiyun #define IMX1_CLK_CLK16M 3 13*4882a593Smuzhiyun #define IMX1_CLK_CLK32_PREMULT 4 14*4882a593Smuzhiyun #define IMX1_CLK_PREM 5 15*4882a593Smuzhiyun #define IMX1_CLK_MPLL 6 16*4882a593Smuzhiyun #define IMX1_CLK_MPLL_GATE 7 17*4882a593Smuzhiyun #define IMX1_CLK_SPLL 8 18*4882a593Smuzhiyun #define IMX1_CLK_SPLL_GATE 9 19*4882a593Smuzhiyun #define IMX1_CLK_MCU 10 20*4882a593Smuzhiyun #define IMX1_CLK_FCLK 11 21*4882a593Smuzhiyun #define IMX1_CLK_HCLK 12 22*4882a593Smuzhiyun #define IMX1_CLK_CLK48M 13 23*4882a593Smuzhiyun #define IMX1_CLK_PER1 14 24*4882a593Smuzhiyun #define IMX1_CLK_PER2 15 25*4882a593Smuzhiyun #define IMX1_CLK_PER3 16 26*4882a593Smuzhiyun #define IMX1_CLK_CLKO 17 27*4882a593Smuzhiyun #define IMX1_CLK_UART3_GATE 18 28*4882a593Smuzhiyun #define IMX1_CLK_SSI2_GATE 19 29*4882a593Smuzhiyun #define IMX1_CLK_BROM_GATE 20 30*4882a593Smuzhiyun #define IMX1_CLK_DMA_GATE 21 31*4882a593Smuzhiyun #define IMX1_CLK_CSI_GATE 22 32*4882a593Smuzhiyun #define IMX1_CLK_MMA_GATE 23 33*4882a593Smuzhiyun #define IMX1_CLK_USBD_GATE 24 34*4882a593Smuzhiyun #define IMX1_CLK_MAX 25 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37