1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Linaro Ltd. 4*4882a593Smuzhiyun * Copyright (c) 2014 Hisilicon Limited. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DTS_HIX5HD2_CLOCK_H 8*4882a593Smuzhiyun #define __DTS_HIX5HD2_CLOCK_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* fixed rate */ 11*4882a593Smuzhiyun #define HIX5HD2_FIXED_1200M 1 12*4882a593Smuzhiyun #define HIX5HD2_FIXED_400M 2 13*4882a593Smuzhiyun #define HIX5HD2_FIXED_48M 3 14*4882a593Smuzhiyun #define HIX5HD2_FIXED_24M 4 15*4882a593Smuzhiyun #define HIX5HD2_FIXED_600M 5 16*4882a593Smuzhiyun #define HIX5HD2_FIXED_300M 6 17*4882a593Smuzhiyun #define HIX5HD2_FIXED_75M 7 18*4882a593Smuzhiyun #define HIX5HD2_FIXED_200M 8 19*4882a593Smuzhiyun #define HIX5HD2_FIXED_100M 9 20*4882a593Smuzhiyun #define HIX5HD2_FIXED_40M 10 21*4882a593Smuzhiyun #define HIX5HD2_FIXED_150M 11 22*4882a593Smuzhiyun #define HIX5HD2_FIXED_1728M 12 23*4882a593Smuzhiyun #define HIX5HD2_FIXED_28P8M 13 24*4882a593Smuzhiyun #define HIX5HD2_FIXED_432M 14 25*4882a593Smuzhiyun #define HIX5HD2_FIXED_345P6M 15 26*4882a593Smuzhiyun #define HIX5HD2_FIXED_288M 16 27*4882a593Smuzhiyun #define HIX5HD2_FIXED_60M 17 28*4882a593Smuzhiyun #define HIX5HD2_FIXED_750M 18 29*4882a593Smuzhiyun #define HIX5HD2_FIXED_500M 19 30*4882a593Smuzhiyun #define HIX5HD2_FIXED_54M 20 31*4882a593Smuzhiyun #define HIX5HD2_FIXED_27M 21 32*4882a593Smuzhiyun #define HIX5HD2_FIXED_1500M 22 33*4882a593Smuzhiyun #define HIX5HD2_FIXED_375M 23 34*4882a593Smuzhiyun #define HIX5HD2_FIXED_187M 24 35*4882a593Smuzhiyun #define HIX5HD2_FIXED_250M 25 36*4882a593Smuzhiyun #define HIX5HD2_FIXED_125M 26 37*4882a593Smuzhiyun #define HIX5HD2_FIXED_2P02M 27 38*4882a593Smuzhiyun #define HIX5HD2_FIXED_50M 28 39*4882a593Smuzhiyun #define HIX5HD2_FIXED_25M 29 40*4882a593Smuzhiyun #define HIX5HD2_FIXED_83M 30 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* mux clocks */ 43*4882a593Smuzhiyun #define HIX5HD2_SFC_MUX 64 44*4882a593Smuzhiyun #define HIX5HD2_MMC_MUX 65 45*4882a593Smuzhiyun #define HIX5HD2_FEPHY_MUX 66 46*4882a593Smuzhiyun #define HIX5HD2_SD_MUX 67 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* gate clocks */ 49*4882a593Smuzhiyun #define HIX5HD2_SFC_RST 128 50*4882a593Smuzhiyun #define HIX5HD2_SFC_CLK 129 51*4882a593Smuzhiyun #define HIX5HD2_MMC_CIU_CLK 130 52*4882a593Smuzhiyun #define HIX5HD2_MMC_BIU_CLK 131 53*4882a593Smuzhiyun #define HIX5HD2_MMC_CIU_RST 132 54*4882a593Smuzhiyun #define HIX5HD2_FWD_BUS_CLK 133 55*4882a593Smuzhiyun #define HIX5HD2_FWD_SYS_CLK 134 56*4882a593Smuzhiyun #define HIX5HD2_MAC0_PHY_CLK 135 57*4882a593Smuzhiyun #define HIX5HD2_SD_CIU_CLK 136 58*4882a593Smuzhiyun #define HIX5HD2_SD_BIU_CLK 137 59*4882a593Smuzhiyun #define HIX5HD2_SD_CIU_RST 138 60*4882a593Smuzhiyun #define HIX5HD2_WDG0_CLK 139 61*4882a593Smuzhiyun #define HIX5HD2_WDG0_RST 140 62*4882a593Smuzhiyun #define HIX5HD2_I2C0_CLK 141 63*4882a593Smuzhiyun #define HIX5HD2_I2C0_RST 142 64*4882a593Smuzhiyun #define HIX5HD2_I2C1_CLK 143 65*4882a593Smuzhiyun #define HIX5HD2_I2C1_RST 144 66*4882a593Smuzhiyun #define HIX5HD2_I2C2_CLK 145 67*4882a593Smuzhiyun #define HIX5HD2_I2C2_RST 146 68*4882a593Smuzhiyun #define HIX5HD2_I2C3_CLK 147 69*4882a593Smuzhiyun #define HIX5HD2_I2C3_RST 148 70*4882a593Smuzhiyun #define HIX5HD2_I2C4_CLK 149 71*4882a593Smuzhiyun #define HIX5HD2_I2C4_RST 150 72*4882a593Smuzhiyun #define HIX5HD2_I2C5_CLK 151 73*4882a593Smuzhiyun #define HIX5HD2_I2C5_RST 152 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* complex */ 76*4882a593Smuzhiyun #define HIX5HD2_MAC0_CLK 192 77*4882a593Smuzhiyun #define HIX5HD2_MAC1_CLK 193 78*4882a593Smuzhiyun #define HIX5HD2_SATA_CLK 194 79*4882a593Smuzhiyun #define HIX5HD2_USB_CLK 195 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define HIX5HD2_NR_CLKS 256 82*4882a593Smuzhiyun #endif /* __DTS_HIX5HD2_CLOCK_H */ 83