1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DTS_HISTB_CLOCK_H 7*4882a593Smuzhiyun #define __DTS_HISTB_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* clocks provided by core CRG */ 10*4882a593Smuzhiyun #define HISTB_OSC_CLK 0 11*4882a593Smuzhiyun #define HISTB_APB_CLK 1 12*4882a593Smuzhiyun #define HISTB_AHB_CLK 2 13*4882a593Smuzhiyun #define HISTB_UART1_CLK 3 14*4882a593Smuzhiyun #define HISTB_UART2_CLK 4 15*4882a593Smuzhiyun #define HISTB_UART3_CLK 5 16*4882a593Smuzhiyun #define HISTB_I2C0_CLK 6 17*4882a593Smuzhiyun #define HISTB_I2C1_CLK 7 18*4882a593Smuzhiyun #define HISTB_I2C2_CLK 8 19*4882a593Smuzhiyun #define HISTB_I2C3_CLK 9 20*4882a593Smuzhiyun #define HISTB_I2C4_CLK 10 21*4882a593Smuzhiyun #define HISTB_I2C5_CLK 11 22*4882a593Smuzhiyun #define HISTB_SPI0_CLK 12 23*4882a593Smuzhiyun #define HISTB_SPI1_CLK 13 24*4882a593Smuzhiyun #define HISTB_SPI2_CLK 14 25*4882a593Smuzhiyun #define HISTB_SCI_CLK 15 26*4882a593Smuzhiyun #define HISTB_FMC_CLK 16 27*4882a593Smuzhiyun #define HISTB_MMC_BIU_CLK 17 28*4882a593Smuzhiyun #define HISTB_MMC_CIU_CLK 18 29*4882a593Smuzhiyun #define HISTB_MMC_DRV_CLK 19 30*4882a593Smuzhiyun #define HISTB_MMC_SAMPLE_CLK 20 31*4882a593Smuzhiyun #define HISTB_SDIO0_BIU_CLK 21 32*4882a593Smuzhiyun #define HISTB_SDIO0_CIU_CLK 22 33*4882a593Smuzhiyun #define HISTB_SDIO0_DRV_CLK 23 34*4882a593Smuzhiyun #define HISTB_SDIO0_SAMPLE_CLK 24 35*4882a593Smuzhiyun #define HISTB_PCIE_AUX_CLK 25 36*4882a593Smuzhiyun #define HISTB_PCIE_PIPE_CLK 26 37*4882a593Smuzhiyun #define HISTB_PCIE_SYS_CLK 27 38*4882a593Smuzhiyun #define HISTB_PCIE_BUS_CLK 28 39*4882a593Smuzhiyun #define HISTB_ETH0_MAC_CLK 29 40*4882a593Smuzhiyun #define HISTB_ETH0_MACIF_CLK 30 41*4882a593Smuzhiyun #define HISTB_ETH1_MAC_CLK 31 42*4882a593Smuzhiyun #define HISTB_ETH1_MACIF_CLK 32 43*4882a593Smuzhiyun #define HISTB_COMBPHY1_CLK 33 44*4882a593Smuzhiyun #define HISTB_USB2_BUS_CLK 34 45*4882a593Smuzhiyun #define HISTB_USB2_PHY_CLK 35 46*4882a593Smuzhiyun #define HISTB_USB2_UTMI_CLK 36 47*4882a593Smuzhiyun #define HISTB_USB2_12M_CLK 37 48*4882a593Smuzhiyun #define HISTB_USB2_48M_CLK 38 49*4882a593Smuzhiyun #define HISTB_USB2_OTG_UTMI_CLK 39 50*4882a593Smuzhiyun #define HISTB_USB2_PHY1_REF_CLK 40 51*4882a593Smuzhiyun #define HISTB_USB2_PHY2_REF_CLK 41 52*4882a593Smuzhiyun #define HISTB_COMBPHY0_CLK 42 53*4882a593Smuzhiyun #define HISTB_USB3_BUS_CLK 43 54*4882a593Smuzhiyun #define HISTB_USB3_UTMI_CLK 44 55*4882a593Smuzhiyun #define HISTB_USB3_PIPE_CLK 45 56*4882a593Smuzhiyun #define HISTB_USB3_SUSPEND_CLK 46 57*4882a593Smuzhiyun #define HISTB_USB3_BUS_CLK1 47 58*4882a593Smuzhiyun #define HISTB_USB3_UTMI_CLK1 48 59*4882a593Smuzhiyun #define HISTB_USB3_PIPE_CLK1 49 60*4882a593Smuzhiyun #define HISTB_USB3_SUSPEND_CLK1 50 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* clocks provided by mcu CRG */ 63*4882a593Smuzhiyun #define HISTB_MCE_CLK 1 64*4882a593Smuzhiyun #define HISTB_IR_CLK 2 65*4882a593Smuzhiyun #define HISTB_TIMER01_CLK 3 66*4882a593Smuzhiyun #define HISTB_LEDC_CLK 4 67*4882a593Smuzhiyun #define HISTB_UART0_CLK 5 68*4882a593Smuzhiyun #define HISTB_LSADC_CLK 6 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __DTS_HISTB_CLOCK_H */ 71