1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree binding constants for HiSilicon Hi3670 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. 6*4882a593Smuzhiyun * Copyright (c) 2018 Linaro Ltd. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_HI3670_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_HI3670_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* clk in stub clock */ 13*4882a593Smuzhiyun #define HI3670_CLK_STUB_CLUSTER0 0 14*4882a593Smuzhiyun #define HI3670_CLK_STUB_CLUSTER1 1 15*4882a593Smuzhiyun #define HI3670_CLK_STUB_GPU 2 16*4882a593Smuzhiyun #define HI3670_CLK_STUB_DDR 3 17*4882a593Smuzhiyun #define HI3670_CLK_STUB_DDR_VOTE 4 18*4882a593Smuzhiyun #define HI3670_CLK_STUB_DDR_LIMIT 5 19*4882a593Smuzhiyun #define HI3670_CLK_STUB_NUM 6 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* clk in crg clock */ 22*4882a593Smuzhiyun #define HI3670_CLKIN_SYS 0 23*4882a593Smuzhiyun #define HI3670_CLKIN_REF 1 24*4882a593Smuzhiyun #define HI3670_CLK_FLL_SRC 2 25*4882a593Smuzhiyun #define HI3670_CLK_PPLL0 3 26*4882a593Smuzhiyun #define HI3670_CLK_PPLL1 4 27*4882a593Smuzhiyun #define HI3670_CLK_PPLL2 5 28*4882a593Smuzhiyun #define HI3670_CLK_PPLL3 6 29*4882a593Smuzhiyun #define HI3670_CLK_PPLL4 7 30*4882a593Smuzhiyun #define HI3670_CLK_PPLL6 8 31*4882a593Smuzhiyun #define HI3670_CLK_PPLL7 9 32*4882a593Smuzhiyun #define HI3670_CLK_PPLL_PCIE 10 33*4882a593Smuzhiyun #define HI3670_CLK_PCIEPLL_REV 11 34*4882a593Smuzhiyun #define HI3670_CLK_SCPLL 12 35*4882a593Smuzhiyun #define HI3670_PCLK 13 36*4882a593Smuzhiyun #define HI3670_CLK_UART0_DBG 14 37*4882a593Smuzhiyun #define HI3670_CLK_UART6 15 38*4882a593Smuzhiyun #define HI3670_OSC32K 16 39*4882a593Smuzhiyun #define HI3670_OSC19M 17 40*4882a593Smuzhiyun #define HI3670_CLK_480M 18 41*4882a593Smuzhiyun #define HI3670_CLK_INVALID 19 42*4882a593Smuzhiyun #define HI3670_CLK_DIV_SYSBUS 20 43*4882a593Smuzhiyun #define HI3670_CLK_FACTOR_MMC 21 44*4882a593Smuzhiyun #define HI3670_CLK_SD_SYS 22 45*4882a593Smuzhiyun #define HI3670_CLK_SDIO_SYS 23 46*4882a593Smuzhiyun #define HI3670_CLK_DIV_A53HPM 24 47*4882a593Smuzhiyun #define HI3670_CLK_DIV_320M 25 48*4882a593Smuzhiyun #define HI3670_PCLK_GATE_UART0 26 49*4882a593Smuzhiyun #define HI3670_CLK_FACTOR_UART0 27 50*4882a593Smuzhiyun #define HI3670_CLK_FACTOR_USB3PHY_PLL 28 51*4882a593Smuzhiyun #define HI3670_CLK_GATE_ABB_USB 29 52*4882a593Smuzhiyun #define HI3670_CLK_GATE_UFSPHY_REF 30 53*4882a593Smuzhiyun #define HI3670_ICS_VOLT_HIGH 31 54*4882a593Smuzhiyun #define HI3670_ICS_VOLT_MIDDLE 32 55*4882a593Smuzhiyun #define HI3670_VENC_VOLT_HOLD 33 56*4882a593Smuzhiyun #define HI3670_VDEC_VOLT_HOLD 34 57*4882a593Smuzhiyun #define HI3670_EDC_VOLT_HOLD 35 58*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_FAC 36 59*4882a593Smuzhiyun #define HI3670_CLK_FACTOR_RXDPHY 37 60*4882a593Smuzhiyun #define HI3670_AUTODIV_SYSBUS 38 61*4882a593Smuzhiyun #define HI3670_AUTODIV_EMMC0BUS 39 62*4882a593Smuzhiyun #define HI3670_PCLK_ANDGT_MMC1_PCIE 40 63*4882a593Smuzhiyun #define HI3670_CLK_GATE_VCODECBUS_GT 41 64*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_SD 42 65*4882a593Smuzhiyun #define HI3670_CLK_SD_SYS_GT 43 66*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_SDIO 44 67*4882a593Smuzhiyun #define HI3670_CLK_SDIO_SYS_GT 45 68*4882a593Smuzhiyun #define HI3670_CLK_A53HPM_ANDGT 46 69*4882a593Smuzhiyun #define HI3670_CLK_320M_PLL_GT 47 70*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_UARTH 48 71*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_UARTL 49 72*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_UART0 50 73*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_SPI 51 74*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_PCIEAXI 52 75*4882a593Smuzhiyun #define HI3670_CLK_DIV_AO_ASP_GT 53 76*4882a593Smuzhiyun #define HI3670_CLK_GATE_CSI_TRANS 54 77*4882a593Smuzhiyun #define HI3670_CLK_GATE_DSI_TRANS 55 78*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_PTP 56 79*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_OUT0 57 80*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_OUT1 58 81*4882a593Smuzhiyun #define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 82*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_VDEC 60 83*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_VENC 61 84*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_ANGT 62 85*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_RXDPHY 63 86*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_ICS 64 87*4882a593Smuzhiyun #define HI3670_AUTODIV_DMABUS 65 88*4882a593Smuzhiyun #define HI3670_CLK_MUX_SYSBUS 66 89*4882a593Smuzhiyun #define HI3670_CLK_MUX_VCODECBUS 67 90*4882a593Smuzhiyun #define HI3670_CLK_MUX_SD_SYS 68 91*4882a593Smuzhiyun #define HI3670_CLK_MUX_SD_PLL 69 92*4882a593Smuzhiyun #define HI3670_CLK_MUX_SDIO_SYS 70 93*4882a593Smuzhiyun #define HI3670_CLK_MUX_SDIO_PLL 71 94*4882a593Smuzhiyun #define HI3670_CLK_MUX_A53HPM 72 95*4882a593Smuzhiyun #define HI3670_CLK_MUX_320M 73 96*4882a593Smuzhiyun #define HI3670_CLK_MUX_UARTH 74 97*4882a593Smuzhiyun #define HI3670_CLK_MUX_UARTL 75 98*4882a593Smuzhiyun #define HI3670_CLK_MUX_UART0 76 99*4882a593Smuzhiyun #define HI3670_CLK_MUX_I2C 77 100*4882a593Smuzhiyun #define HI3670_CLK_MUX_SPI 78 101*4882a593Smuzhiyun #define HI3670_CLK_MUX_PCIEAXI 79 102*4882a593Smuzhiyun #define HI3670_CLK_MUX_AO_ASP 80 103*4882a593Smuzhiyun #define HI3670_CLK_MUX_VDEC 81 104*4882a593Smuzhiyun #define HI3670_CLK_MUX_VENC 82 105*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_MUX0 83 106*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_MUX1 84 107*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_MUX2 85 108*4882a593Smuzhiyun #define HI3670_CLK_MUX_RXDPHY_CFG 86 109*4882a593Smuzhiyun #define HI3670_CLK_MUX_ICS 87 110*4882a593Smuzhiyun #define HI3670_CLK_DIV_CFGBUS 88 111*4882a593Smuzhiyun #define HI3670_CLK_DIV_MMC0BUS 89 112*4882a593Smuzhiyun #define HI3670_CLK_DIV_MMC1BUS 90 113*4882a593Smuzhiyun #define HI3670_PCLK_DIV_MMC1_PCIE 91 114*4882a593Smuzhiyun #define HI3670_CLK_DIV_VCODECBUS 92 115*4882a593Smuzhiyun #define HI3670_CLK_DIV_SD 93 116*4882a593Smuzhiyun #define HI3670_CLK_DIV_SDIO 94 117*4882a593Smuzhiyun #define HI3670_CLK_DIV_UARTH 95 118*4882a593Smuzhiyun #define HI3670_CLK_DIV_UARTL 96 119*4882a593Smuzhiyun #define HI3670_CLK_DIV_UART0 97 120*4882a593Smuzhiyun #define HI3670_CLK_DIV_I2C 98 121*4882a593Smuzhiyun #define HI3670_CLK_DIV_SPI 99 122*4882a593Smuzhiyun #define HI3670_CLK_DIV_PCIEAXI 100 123*4882a593Smuzhiyun #define HI3670_CLK_DIV_AO_ASP 101 124*4882a593Smuzhiyun #define HI3670_CLK_DIV_CSI_TRANS 102 125*4882a593Smuzhiyun #define HI3670_CLK_DIV_DSI_TRANS 103 126*4882a593Smuzhiyun #define HI3670_CLK_DIV_PTP 104 127*4882a593Smuzhiyun #define HI3670_CLK_DIV_CLKOUT0_PLL 105 128*4882a593Smuzhiyun #define HI3670_CLK_DIV_CLKOUT1_PLL 106 129*4882a593Smuzhiyun #define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 130*4882a593Smuzhiyun #define HI3670_CLK_DIV_VDEC 108 131*4882a593Smuzhiyun #define HI3670_CLK_DIV_VENC 109 132*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_DIV0 110 133*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_DIV1 111 134*4882a593Smuzhiyun #define HI3670_CLK_ISP_SNCLK_DIV2 112 135*4882a593Smuzhiyun #define HI3670_CLK_DIV_ICS 113 136*4882a593Smuzhiyun #define HI3670_PPLL1_EN_ACPU 114 137*4882a593Smuzhiyun #define HI3670_PPLL2_EN_ACPU 115 138*4882a593Smuzhiyun #define HI3670_PPLL3_EN_ACPU 116 139*4882a593Smuzhiyun #define HI3670_PPLL1_GT_CPU 117 140*4882a593Smuzhiyun #define HI3670_PPLL2_GT_CPU 118 141*4882a593Smuzhiyun #define HI3670_PPLL3_GT_CPU 119 142*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL2_MEDIA 120 143*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL3_MEDIA 121 144*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL4_MEDIA 122 145*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL6_MEDIA 123 146*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL7_MEDIA 124 147*4882a593Smuzhiyun #define HI3670_PCLK_GPIO0 125 148*4882a593Smuzhiyun #define HI3670_PCLK_GPIO1 126 149*4882a593Smuzhiyun #define HI3670_PCLK_GPIO2 127 150*4882a593Smuzhiyun #define HI3670_PCLK_GPIO3 128 151*4882a593Smuzhiyun #define HI3670_PCLK_GPIO4 129 152*4882a593Smuzhiyun #define HI3670_PCLK_GPIO5 130 153*4882a593Smuzhiyun #define HI3670_PCLK_GPIO6 131 154*4882a593Smuzhiyun #define HI3670_PCLK_GPIO7 132 155*4882a593Smuzhiyun #define HI3670_PCLK_GPIO8 133 156*4882a593Smuzhiyun #define HI3670_PCLK_GPIO9 134 157*4882a593Smuzhiyun #define HI3670_PCLK_GPIO10 135 158*4882a593Smuzhiyun #define HI3670_PCLK_GPIO11 136 159*4882a593Smuzhiyun #define HI3670_PCLK_GPIO12 137 160*4882a593Smuzhiyun #define HI3670_PCLK_GPIO13 138 161*4882a593Smuzhiyun #define HI3670_PCLK_GPIO14 139 162*4882a593Smuzhiyun #define HI3670_PCLK_GPIO15 140 163*4882a593Smuzhiyun #define HI3670_PCLK_GPIO16 141 164*4882a593Smuzhiyun #define HI3670_PCLK_GPIO17 142 165*4882a593Smuzhiyun #define HI3670_PCLK_GPIO20 143 166*4882a593Smuzhiyun #define HI3670_PCLK_GPIO21 144 167*4882a593Smuzhiyun #define HI3670_PCLK_GATE_DSI0 145 168*4882a593Smuzhiyun #define HI3670_PCLK_GATE_DSI1 146 169*4882a593Smuzhiyun #define HI3670_HCLK_GATE_USB3OTG 147 170*4882a593Smuzhiyun #define HI3670_ACLK_GATE_USB3DVFS 148 171*4882a593Smuzhiyun #define HI3670_HCLK_GATE_SDIO 149 172*4882a593Smuzhiyun #define HI3670_PCLK_GATE_PCIE_SYS 150 173*4882a593Smuzhiyun #define HI3670_PCLK_GATE_PCIE_PHY 151 174*4882a593Smuzhiyun #define HI3670_PCLK_GATE_MMC1_PCIE 152 175*4882a593Smuzhiyun #define HI3670_PCLK_GATE_MMC0_IOC 153 176*4882a593Smuzhiyun #define HI3670_PCLK_GATE_MMC1_IOC 154 177*4882a593Smuzhiyun #define HI3670_CLK_GATE_DMAC 155 178*4882a593Smuzhiyun #define HI3670_CLK_GATE_VCODECBUS2DDR 156 179*4882a593Smuzhiyun #define HI3670_CLK_CCI400_BYPASS 157 180*4882a593Smuzhiyun #define HI3670_CLK_GATE_CCI400 158 181*4882a593Smuzhiyun #define HI3670_CLK_GATE_SD 159 182*4882a593Smuzhiyun #define HI3670_HCLK_GATE_SD 160 183*4882a593Smuzhiyun #define HI3670_CLK_GATE_SDIO 161 184*4882a593Smuzhiyun #define HI3670_CLK_GATE_A57HPM 162 185*4882a593Smuzhiyun #define HI3670_CLK_GATE_A53HPM 163 186*4882a593Smuzhiyun #define HI3670_CLK_GATE_PA_A53 164 187*4882a593Smuzhiyun #define HI3670_CLK_GATE_PA_A57 165 188*4882a593Smuzhiyun #define HI3670_CLK_GATE_PA_G3D 166 189*4882a593Smuzhiyun #define HI3670_CLK_GATE_GPUHPM 167 190*4882a593Smuzhiyun #define HI3670_CLK_GATE_PERIHPM 168 191*4882a593Smuzhiyun #define HI3670_CLK_GATE_AOHPM 169 192*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART1 170 193*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART4 171 194*4882a593Smuzhiyun #define HI3670_PCLK_GATE_UART1 172 195*4882a593Smuzhiyun #define HI3670_PCLK_GATE_UART4 173 196*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART2 174 197*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART5 175 198*4882a593Smuzhiyun #define HI3670_PCLK_GATE_UART2 176 199*4882a593Smuzhiyun #define HI3670_PCLK_GATE_UART5 177 200*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART0 178 201*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C3 179 202*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C4 180 203*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C7 181 204*4882a593Smuzhiyun #define HI3670_PCLK_GATE_I2C3 182 205*4882a593Smuzhiyun #define HI3670_PCLK_GATE_I2C4 183 206*4882a593Smuzhiyun #define HI3670_PCLK_GATE_I2C7 184 207*4882a593Smuzhiyun #define HI3670_CLK_GATE_SPI1 185 208*4882a593Smuzhiyun #define HI3670_CLK_GATE_SPI4 186 209*4882a593Smuzhiyun #define HI3670_PCLK_GATE_SPI1 187 210*4882a593Smuzhiyun #define HI3670_PCLK_GATE_SPI4 188 211*4882a593Smuzhiyun #define HI3670_CLK_GATE_USB3OTG_REF 189 212*4882a593Smuzhiyun #define HI3670_CLK_GATE_USB2PHY_REF 190 213*4882a593Smuzhiyun #define HI3670_CLK_GATE_PCIEAUX 191 214*4882a593Smuzhiyun #define HI3670_ACLK_GATE_PCIE 192 215*4882a593Smuzhiyun #define HI3670_CLK_GATE_MMC1_PCIEAXI 193 216*4882a593Smuzhiyun #define HI3670_CLK_GATE_PCIEPHY_REF 194 217*4882a593Smuzhiyun #define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 218*4882a593Smuzhiyun #define HI3670_CLK_GATE_PCIEIO 196 219*4882a593Smuzhiyun #define HI3670_CLK_GATE_PCIE_HP 197 220*4882a593Smuzhiyun #define HI3670_CLK_GATE_AO_ASP 198 221*4882a593Smuzhiyun #define HI3670_PCLK_GATE_PCTRL 199 222*4882a593Smuzhiyun #define HI3670_CLK_CSI_TRANS_GT 200 223*4882a593Smuzhiyun #define HI3670_CLK_DSI_TRANS_GT 201 224*4882a593Smuzhiyun #define HI3670_CLK_GATE_PWM 202 225*4882a593Smuzhiyun #define HI3670_ABB_AUDIO_EN0 203 226*4882a593Smuzhiyun #define HI3670_ABB_AUDIO_EN1 204 227*4882a593Smuzhiyun #define HI3670_ABB_AUDIO_GT_EN0 205 228*4882a593Smuzhiyun #define HI3670_ABB_AUDIO_GT_EN1 206 229*4882a593Smuzhiyun #define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 230*4882a593Smuzhiyun #define HI3670_PERI_VOLT_HOLD 208 231*4882a593Smuzhiyun #define HI3670_PERI_VOLT_MIDDLE 209 232*4882a593Smuzhiyun #define HI3670_CLK_GATE_ISP_SNCLK0 210 233*4882a593Smuzhiyun #define HI3670_CLK_GATE_ISP_SNCLK1 211 234*4882a593Smuzhiyun #define HI3670_CLK_GATE_ISP_SNCLK2 212 235*4882a593Smuzhiyun #define HI3670_CLK_GATE_RXDPHY0_CFG 213 236*4882a593Smuzhiyun #define HI3670_CLK_GATE_RXDPHY1_CFG 214 237*4882a593Smuzhiyun #define HI3670_CLK_GATE_RXDPHY2_CFG 215 238*4882a593Smuzhiyun #define HI3670_CLK_GATE_TXDPHY0_CFG 216 239*4882a593Smuzhiyun #define HI3670_CLK_GATE_TXDPHY0_REF 217 240*4882a593Smuzhiyun #define HI3670_CLK_GATE_TXDPHY1_CFG 218 241*4882a593Smuzhiyun #define HI3670_CLK_GATE_TXDPHY1_REF 219 242*4882a593Smuzhiyun #define HI3670_CLK_GATE_MEDIA_TCXO 220 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* clk in sctrl */ 245*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_IOPERI 0 246*4882a593Smuzhiyun #define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 247*4882a593Smuzhiyun #define HI3670_CLK_ANGT_ASP_SUBSYS 2 248*4882a593Smuzhiyun #define HI3670_CLK_MUX_UFS_SUBSYS 3 249*4882a593Smuzhiyun #define HI3670_CLK_MUX_CLKOUT0 4 250*4882a593Smuzhiyun #define HI3670_CLK_MUX_CLKOUT1 5 251*4882a593Smuzhiyun #define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 252*4882a593Smuzhiyun #define HI3670_CLK_MUX_ASP_PLL 7 253*4882a593Smuzhiyun #define HI3670_CLK_DIV_AOBUS 8 254*4882a593Smuzhiyun #define HI3670_CLK_DIV_UFS_SUBSYS 9 255*4882a593Smuzhiyun #define HI3670_CLK_DIV_IOPERI 10 256*4882a593Smuzhiyun #define HI3670_CLK_DIV_CLKOUT0_TCXO 11 257*4882a593Smuzhiyun #define HI3670_CLK_DIV_CLKOUT1_TCXO 12 258*4882a593Smuzhiyun #define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 259*4882a593Smuzhiyun #define HI3670_CLK_DIV_ASP_SUBSYS 14 260*4882a593Smuzhiyun #define HI3670_PPLL0_EN_ACPU 15 261*4882a593Smuzhiyun #define HI3670_PPLL0_GT_CPU 16 262*4882a593Smuzhiyun #define HI3670_CLK_GATE_PPLL0_MEDIA 17 263*4882a593Smuzhiyun #define HI3670_PCLK_GPIO18 18 264*4882a593Smuzhiyun #define HI3670_PCLK_GPIO19 19 265*4882a593Smuzhiyun #define HI3670_CLK_GATE_SPI 20 266*4882a593Smuzhiyun #define HI3670_PCLK_GATE_SPI 21 267*4882a593Smuzhiyun #define HI3670_CLK_GATE_UFS_SUBSYS 22 268*4882a593Smuzhiyun #define HI3670_CLK_GATE_UFSIO_REF 23 269*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO0 24 270*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO1 25 271*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO2 26 272*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO3 27 273*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO4 28 274*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO5 29 275*4882a593Smuzhiyun #define HI3670_PCLK_AO_GPIO6 30 276*4882a593Smuzhiyun #define HI3670_CLK_GATE_OUT0 31 277*4882a593Smuzhiyun #define HI3670_CLK_GATE_OUT1 32 278*4882a593Smuzhiyun #define HI3670_PCLK_GATE_SYSCNT 33 279*4882a593Smuzhiyun #define HI3670_CLK_GATE_SYSCNT 34 280*4882a593Smuzhiyun #define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 281*4882a593Smuzhiyun #define HI3670_CLK_GATE_ASP_SUBSYS 36 282*4882a593Smuzhiyun #define HI3670_CLK_GATE_ASP_TCXO 37 283*4882a593Smuzhiyun #define HI3670_CLK_GATE_DP_AUDIO_PLL 38 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* clk in pmuctrl */ 286*4882a593Smuzhiyun #define HI3670_GATE_ABB_192 0 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* clk in pctrl */ 289*4882a593Smuzhiyun #define HI3670_GATE_UFS_TCXO_EN 0 290*4882a593Smuzhiyun #define HI3670_GATE_USB_TCXO_EN 1 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* clk in iomcu */ 293*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C0 0 294*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C1 1 295*4882a593Smuzhiyun #define HI3670_CLK_GATE_I2C2 2 296*4882a593Smuzhiyun #define HI3670_CLK_GATE_SPI0 3 297*4882a593Smuzhiyun #define HI3670_CLK_GATE_SPI2 4 298*4882a593Smuzhiyun #define HI3670_CLK_GATE_UART3 5 299*4882a593Smuzhiyun #define HI3670_CLK_I2C0_GATE_IOMCU 6 300*4882a593Smuzhiyun #define HI3670_CLK_I2C1_GATE_IOMCU 7 301*4882a593Smuzhiyun #define HI3670_CLK_I2C2_GATE_IOMCU 8 302*4882a593Smuzhiyun #define HI3670_CLK_SPI0_GATE_IOMCU 9 303*4882a593Smuzhiyun #define HI3670_CLK_SPI2_GATE_IOMCU 10 304*4882a593Smuzhiyun #define HI3670_CLK_UART3_GATE_IOMCU 11 305*4882a593Smuzhiyun #define HI3670_CLK_GATE_PERI0_IOMCU 12 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* clk in media1 */ 308*4882a593Smuzhiyun #define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 309*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_EDC0 1 310*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_LDI0 2 311*4882a593Smuzhiyun #define HI3670_CLK_ANDGT_LDI1 3 312*4882a593Smuzhiyun #define HI3670_CLK_MMBUF_PLL_ANDGT 4 313*4882a593Smuzhiyun #define HI3670_PCLK_MMBUF_ANDGT 5 314*4882a593Smuzhiyun #define HI3670_CLK_MUX_VIVOBUS 6 315*4882a593Smuzhiyun #define HI3670_CLK_MUX_EDC0 7 316*4882a593Smuzhiyun #define HI3670_CLK_MUX_LDI0 8 317*4882a593Smuzhiyun #define HI3670_CLK_MUX_LDI1 9 318*4882a593Smuzhiyun #define HI3670_CLK_SW_MMBUF 10 319*4882a593Smuzhiyun #define HI3670_CLK_DIV_VIVOBUS 11 320*4882a593Smuzhiyun #define HI3670_CLK_DIV_EDC0 12 321*4882a593Smuzhiyun #define HI3670_CLK_DIV_LDI0 13 322*4882a593Smuzhiyun #define HI3670_CLK_DIV_LDI1 14 323*4882a593Smuzhiyun #define HI3670_ACLK_DIV_MMBUF 15 324*4882a593Smuzhiyun #define HI3670_PCLK_DIV_MMBUF 16 325*4882a593Smuzhiyun #define HI3670_ACLK_GATE_NOC_DSS 17 326*4882a593Smuzhiyun #define HI3670_PCLK_GATE_NOC_DSS_CFG 18 327*4882a593Smuzhiyun #define HI3670_PCLK_GATE_MMBUF_CFG 19 328*4882a593Smuzhiyun #define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 329*4882a593Smuzhiyun #define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 330*4882a593Smuzhiyun #define HI3670_PCLK_GATE_DSS 22 331*4882a593Smuzhiyun #define HI3670_ACLK_GATE_DSS 23 332*4882a593Smuzhiyun #define HI3670_CLK_GATE_VIVOBUSFREQ 24 333*4882a593Smuzhiyun #define HI3670_CLK_GATE_EDC0 25 334*4882a593Smuzhiyun #define HI3670_CLK_GATE_LDI0 26 335*4882a593Smuzhiyun #define HI3670_CLK_GATE_LDI1FREQ 27 336*4882a593Smuzhiyun #define HI3670_CLK_GATE_BRG 28 337*4882a593Smuzhiyun #define HI3670_ACLK_GATE_ASC 29 338*4882a593Smuzhiyun #define HI3670_CLK_GATE_DSS_AXI_MM 30 339*4882a593Smuzhiyun #define HI3670_CLK_GATE_MMBUF 31 340*4882a593Smuzhiyun #define HI3670_PCLK_GATE_MMBUF 32 341*4882a593Smuzhiyun #define HI3670_CLK_GATE_ATDIV_VIVO 33 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun /* clk in media2 */ 344*4882a593Smuzhiyun #define HI3670_CLK_GATE_VDECFREQ 0 345*4882a593Smuzhiyun #define HI3670_CLK_GATE_VENCFREQ 1 346*4882a593Smuzhiyun #define HI3670_CLK_GATE_ICSFREQ 2 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_HI3670_H */ 349