1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012-2013 Hisilicon Limited. 4*4882a593Smuzhiyun * Copyright (c) 2012-2013 Linaro Limited. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 7*4882a593Smuzhiyun * Xin Li <li.xin@linaro.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DTS_HI3620_CLOCK_H 11*4882a593Smuzhiyun #define __DTS_HI3620_CLOCK_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define HI3620_NONE_CLOCK 0 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* fixed rate & fixed factor clocks */ 16*4882a593Smuzhiyun #define HI3620_OSC32K 1 17*4882a593Smuzhiyun #define HI3620_OSC26M 2 18*4882a593Smuzhiyun #define HI3620_PCLK 3 19*4882a593Smuzhiyun #define HI3620_PLL_ARM0 4 20*4882a593Smuzhiyun #define HI3620_PLL_ARM1 5 21*4882a593Smuzhiyun #define HI3620_PLL_PERI 6 22*4882a593Smuzhiyun #define HI3620_PLL_USB 7 23*4882a593Smuzhiyun #define HI3620_PLL_HDMI 8 24*4882a593Smuzhiyun #define HI3620_PLL_GPU 9 25*4882a593Smuzhiyun #define HI3620_RCLK_TCXO 10 26*4882a593Smuzhiyun #define HI3620_RCLK_CFGAXI 11 27*4882a593Smuzhiyun #define HI3620_RCLK_PICO 12 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* mux clocks */ 30*4882a593Smuzhiyun #define HI3620_TIMER0_MUX 32 31*4882a593Smuzhiyun #define HI3620_TIMER1_MUX 33 32*4882a593Smuzhiyun #define HI3620_TIMER2_MUX 34 33*4882a593Smuzhiyun #define HI3620_TIMER3_MUX 35 34*4882a593Smuzhiyun #define HI3620_TIMER4_MUX 36 35*4882a593Smuzhiyun #define HI3620_TIMER5_MUX 37 36*4882a593Smuzhiyun #define HI3620_TIMER6_MUX 38 37*4882a593Smuzhiyun #define HI3620_TIMER7_MUX 39 38*4882a593Smuzhiyun #define HI3620_TIMER8_MUX 40 39*4882a593Smuzhiyun #define HI3620_TIMER9_MUX 41 40*4882a593Smuzhiyun #define HI3620_UART0_MUX 42 41*4882a593Smuzhiyun #define HI3620_UART1_MUX 43 42*4882a593Smuzhiyun #define HI3620_UART2_MUX 44 43*4882a593Smuzhiyun #define HI3620_UART3_MUX 45 44*4882a593Smuzhiyun #define HI3620_UART4_MUX 46 45*4882a593Smuzhiyun #define HI3620_SPI0_MUX 47 46*4882a593Smuzhiyun #define HI3620_SPI1_MUX 48 47*4882a593Smuzhiyun #define HI3620_SPI2_MUX 49 48*4882a593Smuzhiyun #define HI3620_SAXI_MUX 50 49*4882a593Smuzhiyun #define HI3620_PWM0_MUX 51 50*4882a593Smuzhiyun #define HI3620_PWM1_MUX 52 51*4882a593Smuzhiyun #define HI3620_SD_MUX 53 52*4882a593Smuzhiyun #define HI3620_MMC1_MUX 54 53*4882a593Smuzhiyun #define HI3620_MMC1_MUX2 55 54*4882a593Smuzhiyun #define HI3620_G2D_MUX 56 55*4882a593Smuzhiyun #define HI3620_VENC_MUX 57 56*4882a593Smuzhiyun #define HI3620_VDEC_MUX 58 57*4882a593Smuzhiyun #define HI3620_VPP_MUX 59 58*4882a593Smuzhiyun #define HI3620_EDC0_MUX 60 59*4882a593Smuzhiyun #define HI3620_LDI0_MUX 61 60*4882a593Smuzhiyun #define HI3620_EDC1_MUX 62 61*4882a593Smuzhiyun #define HI3620_LDI1_MUX 63 62*4882a593Smuzhiyun #define HI3620_RCLK_HSIC 64 63*4882a593Smuzhiyun #define HI3620_MMC2_MUX 65 64*4882a593Smuzhiyun #define HI3620_MMC3_MUX 66 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* divider clocks */ 67*4882a593Smuzhiyun #define HI3620_SHAREAXI_DIV 128 68*4882a593Smuzhiyun #define HI3620_CFGAXI_DIV 129 69*4882a593Smuzhiyun #define HI3620_SD_DIV 130 70*4882a593Smuzhiyun #define HI3620_MMC1_DIV 131 71*4882a593Smuzhiyun #define HI3620_HSIC_DIV 132 72*4882a593Smuzhiyun #define HI3620_MMC2_DIV 133 73*4882a593Smuzhiyun #define HI3620_MMC3_DIV 134 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* gate clocks */ 76*4882a593Smuzhiyun #define HI3620_TIMERCLK01 160 77*4882a593Smuzhiyun #define HI3620_TIMER_RCLK01 161 78*4882a593Smuzhiyun #define HI3620_TIMERCLK23 162 79*4882a593Smuzhiyun #define HI3620_TIMER_RCLK23 163 80*4882a593Smuzhiyun #define HI3620_TIMERCLK45 164 81*4882a593Smuzhiyun #define HI3620_TIMERCLK67 165 82*4882a593Smuzhiyun #define HI3620_TIMERCLK89 166 83*4882a593Smuzhiyun #define HI3620_RTCCLK 167 84*4882a593Smuzhiyun #define HI3620_KPC_CLK 168 85*4882a593Smuzhiyun #define HI3620_GPIOCLK0 169 86*4882a593Smuzhiyun #define HI3620_GPIOCLK1 170 87*4882a593Smuzhiyun #define HI3620_GPIOCLK2 171 88*4882a593Smuzhiyun #define HI3620_GPIOCLK3 172 89*4882a593Smuzhiyun #define HI3620_GPIOCLK4 173 90*4882a593Smuzhiyun #define HI3620_GPIOCLK5 174 91*4882a593Smuzhiyun #define HI3620_GPIOCLK6 175 92*4882a593Smuzhiyun #define HI3620_GPIOCLK7 176 93*4882a593Smuzhiyun #define HI3620_GPIOCLK8 177 94*4882a593Smuzhiyun #define HI3620_GPIOCLK9 178 95*4882a593Smuzhiyun #define HI3620_GPIOCLK10 179 96*4882a593Smuzhiyun #define HI3620_GPIOCLK11 180 97*4882a593Smuzhiyun #define HI3620_GPIOCLK12 181 98*4882a593Smuzhiyun #define HI3620_GPIOCLK13 182 99*4882a593Smuzhiyun #define HI3620_GPIOCLK14 183 100*4882a593Smuzhiyun #define HI3620_GPIOCLK15 184 101*4882a593Smuzhiyun #define HI3620_GPIOCLK16 185 102*4882a593Smuzhiyun #define HI3620_GPIOCLK17 186 103*4882a593Smuzhiyun #define HI3620_GPIOCLK18 187 104*4882a593Smuzhiyun #define HI3620_GPIOCLK19 188 105*4882a593Smuzhiyun #define HI3620_GPIOCLK20 189 106*4882a593Smuzhiyun #define HI3620_GPIOCLK21 190 107*4882a593Smuzhiyun #define HI3620_DPHY0_CLK 191 108*4882a593Smuzhiyun #define HI3620_DPHY1_CLK 192 109*4882a593Smuzhiyun #define HI3620_DPHY2_CLK 193 110*4882a593Smuzhiyun #define HI3620_USBPHY_CLK 194 111*4882a593Smuzhiyun #define HI3620_ACP_CLK 195 112*4882a593Smuzhiyun #define HI3620_PWMCLK0 196 113*4882a593Smuzhiyun #define HI3620_PWMCLK1 197 114*4882a593Smuzhiyun #define HI3620_UARTCLK0 198 115*4882a593Smuzhiyun #define HI3620_UARTCLK1 199 116*4882a593Smuzhiyun #define HI3620_UARTCLK2 200 117*4882a593Smuzhiyun #define HI3620_UARTCLK3 201 118*4882a593Smuzhiyun #define HI3620_UARTCLK4 202 119*4882a593Smuzhiyun #define HI3620_SPICLK0 203 120*4882a593Smuzhiyun #define HI3620_SPICLK1 204 121*4882a593Smuzhiyun #define HI3620_SPICLK2 205 122*4882a593Smuzhiyun #define HI3620_I2CCLK0 206 123*4882a593Smuzhiyun #define HI3620_I2CCLK1 207 124*4882a593Smuzhiyun #define HI3620_I2CCLK2 208 125*4882a593Smuzhiyun #define HI3620_I2CCLK3 209 126*4882a593Smuzhiyun #define HI3620_SCI_CLK 210 127*4882a593Smuzhiyun #define HI3620_DDRC_PER_CLK 211 128*4882a593Smuzhiyun #define HI3620_DMAC_CLK 212 129*4882a593Smuzhiyun #define HI3620_USB2DVC_CLK 213 130*4882a593Smuzhiyun #define HI3620_SD_CLK 214 131*4882a593Smuzhiyun #define HI3620_MMC_CLK1 215 132*4882a593Smuzhiyun #define HI3620_MMC_CLK2 216 133*4882a593Smuzhiyun #define HI3620_MMC_CLK3 217 134*4882a593Smuzhiyun #define HI3620_MCU_CLK 218 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define HI3620_SD_CIUCLK 0 137*4882a593Smuzhiyun #define HI3620_MMC_CIUCLK1 1 138*4882a593Smuzhiyun #define HI3620_MMC_CIUCLK2 2 139*4882a593Smuzhiyun #define HI3620_MMC_CIUCLK3 3 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define HI3620_NR_CLKS 219 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /* __DTS_HI3620_CLOCK_H */ 144