1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DTS_HI3519_CLOCK_H 7*4882a593Smuzhiyun #define __DTS_HI3519_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HI3519_FMC_CLK 1 10*4882a593Smuzhiyun #define HI3519_SPI0_CLK 2 11*4882a593Smuzhiyun #define HI3519_SPI1_CLK 3 12*4882a593Smuzhiyun #define HI3519_SPI2_CLK 4 13*4882a593Smuzhiyun #define HI3519_UART0_CLK 5 14*4882a593Smuzhiyun #define HI3519_UART1_CLK 6 15*4882a593Smuzhiyun #define HI3519_UART2_CLK 7 16*4882a593Smuzhiyun #define HI3519_UART3_CLK 8 17*4882a593Smuzhiyun #define HI3519_UART4_CLK 9 18*4882a593Smuzhiyun #define HI3519_PWM_CLK 10 19*4882a593Smuzhiyun #define HI3519_DMA_CLK 11 20*4882a593Smuzhiyun #define HI3519_IR_CLK 12 21*4882a593Smuzhiyun #define HI3519_ETH_PHY_CLK 13 22*4882a593Smuzhiyun #define HI3519_ETH_MAC_CLK 14 23*4882a593Smuzhiyun #define HI3519_ETH_MACIF_CLK 15 24*4882a593Smuzhiyun #define HI3519_USB2_BUS_CLK 16 25*4882a593Smuzhiyun #define HI3519_USB2_PORT_CLK 17 26*4882a593Smuzhiyun #define HI3519_USB3_CLK 18 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __DTS_HI3519_CLOCK_H */ 29