1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DTS_HI3516CV300_CLOCK_H 7*4882a593Smuzhiyun #define __DTS_HI3516CV300_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* hi3516CV300 core CRG */ 10*4882a593Smuzhiyun #define HI3516CV300_APB_CLK 0 11*4882a593Smuzhiyun #define HI3516CV300_UART0_CLK 1 12*4882a593Smuzhiyun #define HI3516CV300_UART1_CLK 2 13*4882a593Smuzhiyun #define HI3516CV300_UART2_CLK 3 14*4882a593Smuzhiyun #define HI3516CV300_SPI0_CLK 4 15*4882a593Smuzhiyun #define HI3516CV300_SPI1_CLK 5 16*4882a593Smuzhiyun #define HI3516CV300_FMC_CLK 6 17*4882a593Smuzhiyun #define HI3516CV300_MMC0_CLK 7 18*4882a593Smuzhiyun #define HI3516CV300_MMC1_CLK 8 19*4882a593Smuzhiyun #define HI3516CV300_MMC2_CLK 9 20*4882a593Smuzhiyun #define HI3516CV300_MMC3_CLK 10 21*4882a593Smuzhiyun #define HI3516CV300_ETH_CLK 11 22*4882a593Smuzhiyun #define HI3516CV300_ETH_MACIF_CLK 12 23*4882a593Smuzhiyun #define HI3516CV300_DMAC_CLK 13 24*4882a593Smuzhiyun #define HI3516CV300_PWM_CLK 14 25*4882a593Smuzhiyun #define HI3516CV300_USB2_BUS_CLK 15 26*4882a593Smuzhiyun #define HI3516CV300_USB2_OHCI48M_CLK 16 27*4882a593Smuzhiyun #define HI3516CV300_USB2_OHCI12M_CLK 17 28*4882a593Smuzhiyun #define HI3516CV300_USB2_OTG_UTMI_CLK 18 29*4882a593Smuzhiyun #define HI3516CV300_USB2_HST_PHY_CLK 19 30*4882a593Smuzhiyun #define HI3516CV300_USB2_UTMI0_CLK 20 31*4882a593Smuzhiyun #define HI3516CV300_USB2_PHY_CLK 21 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* hi3516CV300 sysctrl CRG */ 34*4882a593Smuzhiyun #define HI3516CV300_WDT_CLK 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __DTS_HI3516CV300_CLOCK_H */ 37