1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * GXBB clock tree IDs 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __GXBB_CLKC_H 7*4882a593Smuzhiyun #define __GXBB_CLKC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLKID_SYS_PLL 0 10*4882a593Smuzhiyun #define CLKID_HDMI_PLL 2 11*4882a593Smuzhiyun #define CLKID_FIXED_PLL 3 12*4882a593Smuzhiyun #define CLKID_FCLK_DIV2 4 13*4882a593Smuzhiyun #define CLKID_FCLK_DIV3 5 14*4882a593Smuzhiyun #define CLKID_FCLK_DIV4 6 15*4882a593Smuzhiyun #define CLKID_FCLK_DIV5 7 16*4882a593Smuzhiyun #define CLKID_FCLK_DIV7 8 17*4882a593Smuzhiyun #define CLKID_GP0_PLL 9 18*4882a593Smuzhiyun #define CLKID_CLK81 12 19*4882a593Smuzhiyun #define CLKID_MPLL0 13 20*4882a593Smuzhiyun #define CLKID_MPLL1 14 21*4882a593Smuzhiyun #define CLKID_MPLL2 15 22*4882a593Smuzhiyun #define CLKID_DDR 16 23*4882a593Smuzhiyun #define CLKID_DOS 17 24*4882a593Smuzhiyun #define CLKID_ISA 18 25*4882a593Smuzhiyun #define CLKID_PL301 19 26*4882a593Smuzhiyun #define CLKID_PERIPHS 20 27*4882a593Smuzhiyun #define CLKID_SPICC 21 28*4882a593Smuzhiyun #define CLKID_I2C 22 29*4882a593Smuzhiyun #define CLKID_SAR_ADC 23 30*4882a593Smuzhiyun #define CLKID_SMART_CARD 24 31*4882a593Smuzhiyun #define CLKID_RNG0 25 32*4882a593Smuzhiyun #define CLKID_UART0 26 33*4882a593Smuzhiyun #define CLKID_SDHC 27 34*4882a593Smuzhiyun #define CLKID_STREAM 28 35*4882a593Smuzhiyun #define CLKID_ASYNC_FIFO 29 36*4882a593Smuzhiyun #define CLKID_SDIO 30 37*4882a593Smuzhiyun #define CLKID_ABUF 31 38*4882a593Smuzhiyun #define CLKID_HIU_IFACE 32 39*4882a593Smuzhiyun #define CLKID_ASSIST_MISC 33 40*4882a593Smuzhiyun #define CLKID_SPI 34 41*4882a593Smuzhiyun #define CLKID_ETH 36 42*4882a593Smuzhiyun #define CLKID_I2S_SPDIF 35 43*4882a593Smuzhiyun #define CLKID_DEMUX 37 44*4882a593Smuzhiyun #define CLKID_AIU_GLUE 38 45*4882a593Smuzhiyun #define CLKID_IEC958 39 46*4882a593Smuzhiyun #define CLKID_I2S_OUT 40 47*4882a593Smuzhiyun #define CLKID_AMCLK 41 48*4882a593Smuzhiyun #define CLKID_AIFIFO2 42 49*4882a593Smuzhiyun #define CLKID_MIXER 43 50*4882a593Smuzhiyun #define CLKID_MIXER_IFACE 44 51*4882a593Smuzhiyun #define CLKID_ADC 45 52*4882a593Smuzhiyun #define CLKID_BLKMV 46 53*4882a593Smuzhiyun #define CLKID_AIU 47 54*4882a593Smuzhiyun #define CLKID_UART1 48 55*4882a593Smuzhiyun #define CLKID_G2D 49 56*4882a593Smuzhiyun #define CLKID_USB0 50 57*4882a593Smuzhiyun #define CLKID_USB1 51 58*4882a593Smuzhiyun #define CLKID_RESET 52 59*4882a593Smuzhiyun #define CLKID_NAND 53 60*4882a593Smuzhiyun #define CLKID_DOS_PARSER 54 61*4882a593Smuzhiyun #define CLKID_USB 55 62*4882a593Smuzhiyun #define CLKID_VDIN1 56 63*4882a593Smuzhiyun #define CLKID_AHB_ARB0 57 64*4882a593Smuzhiyun #define CLKID_EFUSE 58 65*4882a593Smuzhiyun #define CLKID_BOOT_ROM 59 66*4882a593Smuzhiyun #define CLKID_AHB_DATA_BUS 60 67*4882a593Smuzhiyun #define CLKID_AHB_CTRL_BUS 61 68*4882a593Smuzhiyun #define CLKID_HDMI_INTR_SYNC 62 69*4882a593Smuzhiyun #define CLKID_HDMI_PCLK 63 70*4882a593Smuzhiyun #define CLKID_USB1_DDR_BRIDGE 64 71*4882a593Smuzhiyun #define CLKID_USB0_DDR_BRIDGE 65 72*4882a593Smuzhiyun #define CLKID_MMC_PCLK 66 73*4882a593Smuzhiyun #define CLKID_DVIN 67 74*4882a593Smuzhiyun #define CLKID_UART2 68 75*4882a593Smuzhiyun #define CLKID_SANA 69 76*4882a593Smuzhiyun #define CLKID_VPU_INTR 70 77*4882a593Smuzhiyun #define CLKID_SEC_AHB_AHB3_BRIDGE 71 78*4882a593Smuzhiyun #define CLKID_CLK81_A53 72 79*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI0 73 80*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI1 74 81*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP0 75 82*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP1 76 83*4882a593Smuzhiyun #define CLKID_GCLK_VENCI_INT0 77 84*4882a593Smuzhiyun #define CLKID_GCLK_VENCI_INT 78 85*4882a593Smuzhiyun #define CLKID_DAC_CLK 79 86*4882a593Smuzhiyun #define CLKID_AOCLK_GATE 80 87*4882a593Smuzhiyun #define CLKID_IEC958_GATE 81 88*4882a593Smuzhiyun #define CLKID_ENC480P 82 89*4882a593Smuzhiyun #define CLKID_RNG1 83 90*4882a593Smuzhiyun #define CLKID_GCLK_VENCI_INT1 84 91*4882a593Smuzhiyun #define CLKID_VCLK2_VENCLMCC 85 92*4882a593Smuzhiyun #define CLKID_VCLK2_VENCL 86 93*4882a593Smuzhiyun #define CLKID_VCLK_OTHER 87 94*4882a593Smuzhiyun #define CLKID_EDP 88 95*4882a593Smuzhiyun #define CLKID_AO_MEDIA_CPU 89 96*4882a593Smuzhiyun #define CLKID_AO_AHB_SRAM 90 97*4882a593Smuzhiyun #define CLKID_AO_AHB_BUS 91 98*4882a593Smuzhiyun #define CLKID_AO_IFACE 92 99*4882a593Smuzhiyun #define CLKID_AO_I2C 93 100*4882a593Smuzhiyun #define CLKID_SD_EMMC_A 94 101*4882a593Smuzhiyun #define CLKID_SD_EMMC_B 95 102*4882a593Smuzhiyun #define CLKID_SD_EMMC_C 96 103*4882a593Smuzhiyun #define CLKID_SAR_ADC_CLK 97 104*4882a593Smuzhiyun #define CLKID_SAR_ADC_SEL 98 105*4882a593Smuzhiyun #define CLKID_MALI_0_SEL 100 106*4882a593Smuzhiyun #define CLKID_MALI_0 102 107*4882a593Smuzhiyun #define CLKID_MALI_1_SEL 103 108*4882a593Smuzhiyun #define CLKID_MALI_1 105 109*4882a593Smuzhiyun #define CLKID_MALI 106 110*4882a593Smuzhiyun #define CLKID_CTS_AMCLK 107 111*4882a593Smuzhiyun #define CLKID_CTS_MCLK_I958 110 112*4882a593Smuzhiyun #define CLKID_CTS_I958 113 113*4882a593Smuzhiyun #define CLKID_32K_CLK 114 114*4882a593Smuzhiyun #define CLKID_SD_EMMC_A_CLK0 119 115*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0 122 116*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0 125 117*4882a593Smuzhiyun #define CLKID_VPU_0_SEL 126 118*4882a593Smuzhiyun #define CLKID_VPU_0 128 119*4882a593Smuzhiyun #define CLKID_VPU_1_SEL 129 120*4882a593Smuzhiyun #define CLKID_VPU_1 131 121*4882a593Smuzhiyun #define CLKID_VPU 132 122*4882a593Smuzhiyun #define CLKID_VAPB_0_SEL 133 123*4882a593Smuzhiyun #define CLKID_VAPB_0 135 124*4882a593Smuzhiyun #define CLKID_VAPB_1_SEL 136 125*4882a593Smuzhiyun #define CLKID_VAPB_1 138 126*4882a593Smuzhiyun #define CLKID_VAPB_SEL 139 127*4882a593Smuzhiyun #define CLKID_VAPB 140 128*4882a593Smuzhiyun #define CLKID_VDEC_1 153 129*4882a593Smuzhiyun #define CLKID_VDEC_HEVC 156 130*4882a593Smuzhiyun #define CLKID_GEN_CLK 159 131*4882a593Smuzhiyun #define CLKID_VID_PLL 166 132*4882a593Smuzhiyun #define CLKID_VCLK 175 133*4882a593Smuzhiyun #define CLKID_VCLK2 176 134*4882a593Smuzhiyun #define CLKID_VCLK_DIV1 185 135*4882a593Smuzhiyun #define CLKID_VCLK_DIV2 186 136*4882a593Smuzhiyun #define CLKID_VCLK_DIV4 187 137*4882a593Smuzhiyun #define CLKID_VCLK_DIV6 188 138*4882a593Smuzhiyun #define CLKID_VCLK_DIV12 189 139*4882a593Smuzhiyun #define CLKID_VCLK2_DIV1 190 140*4882a593Smuzhiyun #define CLKID_VCLK2_DIV2 191 141*4882a593Smuzhiyun #define CLKID_VCLK2_DIV4 192 142*4882a593Smuzhiyun #define CLKID_VCLK2_DIV6 193 143*4882a593Smuzhiyun #define CLKID_VCLK2_DIV12 194 144*4882a593Smuzhiyun #define CLKID_CTS_ENCI 199 145*4882a593Smuzhiyun #define CLKID_CTS_ENCP 200 146*4882a593Smuzhiyun #define CLKID_CTS_VDAC 201 147*4882a593Smuzhiyun #define CLKID_HDMI_TX 202 148*4882a593Smuzhiyun #define CLKID_HDMI 205 149*4882a593Smuzhiyun #define CLKID_ACODEC 206 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif /* __GXBB_CLKC_H */ 152