1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Meson-G12A clock tree IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __G12A_CLKC_H 9*4882a593Smuzhiyun #define __G12A_CLKC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLKID_SYS_PLL 0 12*4882a593Smuzhiyun #define CLKID_FIXED_PLL 1 13*4882a593Smuzhiyun #define CLKID_FCLK_DIV2 2 14*4882a593Smuzhiyun #define CLKID_FCLK_DIV3 3 15*4882a593Smuzhiyun #define CLKID_FCLK_DIV4 4 16*4882a593Smuzhiyun #define CLKID_FCLK_DIV5 5 17*4882a593Smuzhiyun #define CLKID_FCLK_DIV7 6 18*4882a593Smuzhiyun #define CLKID_GP0_PLL 7 19*4882a593Smuzhiyun #define CLKID_CLK81 10 20*4882a593Smuzhiyun #define CLKID_MPLL0 11 21*4882a593Smuzhiyun #define CLKID_MPLL1 12 22*4882a593Smuzhiyun #define CLKID_MPLL2 13 23*4882a593Smuzhiyun #define CLKID_MPLL3 14 24*4882a593Smuzhiyun #define CLKID_DDR 15 25*4882a593Smuzhiyun #define CLKID_DOS 16 26*4882a593Smuzhiyun #define CLKID_AUDIO_LOCKER 17 27*4882a593Smuzhiyun #define CLKID_MIPI_DSI_HOST 18 28*4882a593Smuzhiyun #define CLKID_ETH_PHY 19 29*4882a593Smuzhiyun #define CLKID_ISA 20 30*4882a593Smuzhiyun #define CLKID_PL301 21 31*4882a593Smuzhiyun #define CLKID_PERIPHS 22 32*4882a593Smuzhiyun #define CLKID_SPICC0 23 33*4882a593Smuzhiyun #define CLKID_I2C 24 34*4882a593Smuzhiyun #define CLKID_SANA 25 35*4882a593Smuzhiyun #define CLKID_SD 26 36*4882a593Smuzhiyun #define CLKID_RNG0 27 37*4882a593Smuzhiyun #define CLKID_UART0 28 38*4882a593Smuzhiyun #define CLKID_SPICC1 29 39*4882a593Smuzhiyun #define CLKID_HIU_IFACE 30 40*4882a593Smuzhiyun #define CLKID_MIPI_DSI_PHY 31 41*4882a593Smuzhiyun #define CLKID_ASSIST_MISC 32 42*4882a593Smuzhiyun #define CLKID_SD_EMMC_A 33 43*4882a593Smuzhiyun #define CLKID_SD_EMMC_B 34 44*4882a593Smuzhiyun #define CLKID_SD_EMMC_C 35 45*4882a593Smuzhiyun #define CLKID_AUDIO_CODEC 36 46*4882a593Smuzhiyun #define CLKID_AUDIO 37 47*4882a593Smuzhiyun #define CLKID_ETH 38 48*4882a593Smuzhiyun #define CLKID_DEMUX 39 49*4882a593Smuzhiyun #define CLKID_AUDIO_IFIFO 40 50*4882a593Smuzhiyun #define CLKID_ADC 41 51*4882a593Smuzhiyun #define CLKID_UART1 42 52*4882a593Smuzhiyun #define CLKID_G2D 43 53*4882a593Smuzhiyun #define CLKID_RESET 44 54*4882a593Smuzhiyun #define CLKID_PCIE_COMB 45 55*4882a593Smuzhiyun #define CLKID_PARSER 46 56*4882a593Smuzhiyun #define CLKID_USB 47 57*4882a593Smuzhiyun #define CLKID_PCIE_PHY 48 58*4882a593Smuzhiyun #define CLKID_AHB_ARB0 49 59*4882a593Smuzhiyun #define CLKID_AHB_DATA_BUS 50 60*4882a593Smuzhiyun #define CLKID_AHB_CTRL_BUS 51 61*4882a593Smuzhiyun #define CLKID_HTX_HDCP22 52 62*4882a593Smuzhiyun #define CLKID_HTX_PCLK 53 63*4882a593Smuzhiyun #define CLKID_BT656 54 64*4882a593Smuzhiyun #define CLKID_USB1_DDR_BRIDGE 55 65*4882a593Smuzhiyun #define CLKID_MMC_PCLK 56 66*4882a593Smuzhiyun #define CLKID_UART2 57 67*4882a593Smuzhiyun #define CLKID_VPU_INTR 58 68*4882a593Smuzhiyun #define CLKID_GIC 59 69*4882a593Smuzhiyun #define CLKID_SD_EMMC_A_CLK0 60 70*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0 61 71*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0 62 72*4882a593Smuzhiyun #define CLKID_HIFI_PLL 74 73*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI0 80 74*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI1 81 75*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP0 82 76*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP1 83 77*4882a593Smuzhiyun #define CLKID_VCLK2_VENCT0 84 78*4882a593Smuzhiyun #define CLKID_VCLK2_VENCT1 85 79*4882a593Smuzhiyun #define CLKID_VCLK2_OTHER 86 80*4882a593Smuzhiyun #define CLKID_VCLK2_ENCI 87 81*4882a593Smuzhiyun #define CLKID_VCLK2_ENCP 88 82*4882a593Smuzhiyun #define CLKID_DAC_CLK 89 83*4882a593Smuzhiyun #define CLKID_AOCLK 90 84*4882a593Smuzhiyun #define CLKID_IEC958 91 85*4882a593Smuzhiyun #define CLKID_ENC480P 92 86*4882a593Smuzhiyun #define CLKID_RNG1 93 87*4882a593Smuzhiyun #define CLKID_VCLK2_ENCT 94 88*4882a593Smuzhiyun #define CLKID_VCLK2_ENCL 95 89*4882a593Smuzhiyun #define CLKID_VCLK2_VENCLMMC 96 90*4882a593Smuzhiyun #define CLKID_VCLK2_VENCL 97 91*4882a593Smuzhiyun #define CLKID_VCLK2_OTHER1 98 92*4882a593Smuzhiyun #define CLKID_FCLK_DIV2P5 99 93*4882a593Smuzhiyun #define CLKID_DMA 105 94*4882a593Smuzhiyun #define CLKID_EFUSE 106 95*4882a593Smuzhiyun #define CLKID_ROM_BOOT 107 96*4882a593Smuzhiyun #define CLKID_RESET_SEC 108 97*4882a593Smuzhiyun #define CLKID_SEC_AHB_APB3 109 98*4882a593Smuzhiyun #define CLKID_VPU_0_SEL 110 99*4882a593Smuzhiyun #define CLKID_VPU_0 112 100*4882a593Smuzhiyun #define CLKID_VPU_1_SEL 113 101*4882a593Smuzhiyun #define CLKID_VPU_1 115 102*4882a593Smuzhiyun #define CLKID_VPU 116 103*4882a593Smuzhiyun #define CLKID_VAPB_0_SEL 117 104*4882a593Smuzhiyun #define CLKID_VAPB_0 119 105*4882a593Smuzhiyun #define CLKID_VAPB_1_SEL 120 106*4882a593Smuzhiyun #define CLKID_VAPB_1 122 107*4882a593Smuzhiyun #define CLKID_VAPB_SEL 123 108*4882a593Smuzhiyun #define CLKID_VAPB 124 109*4882a593Smuzhiyun #define CLKID_HDMI_PLL 128 110*4882a593Smuzhiyun #define CLKID_VID_PLL 129 111*4882a593Smuzhiyun #define CLKID_VCLK 138 112*4882a593Smuzhiyun #define CLKID_VCLK2 139 113*4882a593Smuzhiyun #define CLKID_VCLK_DIV1 148 114*4882a593Smuzhiyun #define CLKID_VCLK_DIV2 149 115*4882a593Smuzhiyun #define CLKID_VCLK_DIV4 150 116*4882a593Smuzhiyun #define CLKID_VCLK_DIV6 151 117*4882a593Smuzhiyun #define CLKID_VCLK_DIV12 152 118*4882a593Smuzhiyun #define CLKID_VCLK2_DIV1 153 119*4882a593Smuzhiyun #define CLKID_VCLK2_DIV2 154 120*4882a593Smuzhiyun #define CLKID_VCLK2_DIV4 155 121*4882a593Smuzhiyun #define CLKID_VCLK2_DIV6 156 122*4882a593Smuzhiyun #define CLKID_VCLK2_DIV12 157 123*4882a593Smuzhiyun #define CLKID_CTS_ENCI 162 124*4882a593Smuzhiyun #define CLKID_CTS_ENCP 163 125*4882a593Smuzhiyun #define CLKID_CTS_VDAC 164 126*4882a593Smuzhiyun #define CLKID_HDMI_TX 165 127*4882a593Smuzhiyun #define CLKID_HDMI 168 128*4882a593Smuzhiyun #define CLKID_MALI_0_SEL 169 129*4882a593Smuzhiyun #define CLKID_MALI_0 171 130*4882a593Smuzhiyun #define CLKID_MALI_1_SEL 172 131*4882a593Smuzhiyun #define CLKID_MALI_1 174 132*4882a593Smuzhiyun #define CLKID_MALI 175 133*4882a593Smuzhiyun #define CLKID_MPLL_50M 177 134*4882a593Smuzhiyun #define CLKID_CPU_CLK 187 135*4882a593Smuzhiyun #define CLKID_PCIE_PLL 201 136*4882a593Smuzhiyun #define CLKID_VDEC_1 204 137*4882a593Smuzhiyun #define CLKID_VDEC_HEVC 207 138*4882a593Smuzhiyun #define CLKID_VDEC_HEVCF 210 139*4882a593Smuzhiyun #define CLKID_TS 212 140*4882a593Smuzhiyun #define CLKID_CPUB_CLK 224 141*4882a593Smuzhiyun #define CLKID_GP1_PLL 243 142*4882a593Smuzhiyun #define CLKID_DSU_CLK 252 143*4882a593Smuzhiyun #define CLKID_CPU1_CLK 253 144*4882a593Smuzhiyun #define CLKID_CPU2_CLK 254 145*4882a593Smuzhiyun #define CLKID_CPU3_CLK 255 146*4882a593Smuzhiyun #define CLKID_SPICC0_SCLK 258 147*4882a593Smuzhiyun #define CLKID_SPICC1_SCLK 261 148*4882a593Smuzhiyun #define CLKID_NNA_AXI_CLK 264 149*4882a593Smuzhiyun #define CLKID_NNA_CORE_CLK 267 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif /* __G12A_CLKC_H */ 152