1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Rahul Sharma <rahul.sharma@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Provides Constants for Exynos5260 clocks. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_EXYNOS5260_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Clock names: <cmu><type><IP> */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* List Of Clocks For CMU_TOP */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define TOP_FOUT_DISP_PLL 1 17*4882a593Smuzhiyun #define TOP_FOUT_AUD_PLL 2 18*4882a593Smuzhiyun #define TOP_MOUT_AUDTOP_PLL_USER 3 19*4882a593Smuzhiyun #define TOP_MOUT_AUD_PLL 4 20*4882a593Smuzhiyun #define TOP_MOUT_DISP_PLL 5 21*4882a593Smuzhiyun #define TOP_MOUT_BUSTOP_PLL_USER 6 22*4882a593Smuzhiyun #define TOP_MOUT_MEMTOP_PLL_USER 7 23*4882a593Smuzhiyun #define TOP_MOUT_MEDIATOP_PLL_USER 8 24*4882a593Smuzhiyun #define TOP_MOUT_DISP_DISP_333 9 25*4882a593Smuzhiyun #define TOP_MOUT_ACLK_DISP_333 10 26*4882a593Smuzhiyun #define TOP_MOUT_DISP_DISP_222 11 27*4882a593Smuzhiyun #define TOP_MOUT_ACLK_DISP_222 12 28*4882a593Smuzhiyun #define TOP_MOUT_DISP_MEDIA_PIXEL 13 29*4882a593Smuzhiyun #define TOP_MOUT_FIMD1 14 30*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 31*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 32*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 33*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 34*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 35*4882a593Smuzhiyun #define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 36*4882a593Smuzhiyun #define TOP_MOUT_BUS4_BUSTOP_100 21 37*4882a593Smuzhiyun #define TOP_MOUT_BUS4_BUSTOP_400 22 38*4882a593Smuzhiyun #define TOP_MOUT_BUS3_BUSTOP_100 23 39*4882a593Smuzhiyun #define TOP_MOUT_BUS3_BUSTOP_400 24 40*4882a593Smuzhiyun #define TOP_MOUT_BUS2_BUSTOP_400 25 41*4882a593Smuzhiyun #define TOP_MOUT_BUS2_BUSTOP_100 26 42*4882a593Smuzhiyun #define TOP_MOUT_BUS1_BUSTOP_100 27 43*4882a593Smuzhiyun #define TOP_MOUT_BUS1_BUSTOP_400 28 44*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_USB 29 45*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 46*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 47*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 48*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 49*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 50*4882a593Smuzhiyun #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 51*4882a593Smuzhiyun #define TOP_MOUT_ACLK_ISP1_266 36 52*4882a593Smuzhiyun #define TOP_MOUT_ISP1_MEDIA_266 37 53*4882a593Smuzhiyun #define TOP_MOUT_ACLK_ISP1_400 38 54*4882a593Smuzhiyun #define TOP_MOUT_ISP1_MEDIA_400 39 55*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_SPI0 40 56*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_SPI1 41 57*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_UART 42 58*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_SENSOR2 43 59*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_SENSOR1 44 60*4882a593Smuzhiyun #define TOP_MOUT_SCLK_ISP1_SENSOR0 45 61*4882a593Smuzhiyun #define TOP_MOUT_ACLK_MFC_333 46 62*4882a593Smuzhiyun #define TOP_MOUT_MFC_BUSTOP_333 47 63*4882a593Smuzhiyun #define TOP_MOUT_ACLK_G2D_333 48 64*4882a593Smuzhiyun #define TOP_MOUT_G2D_BUSTOP_333 49 65*4882a593Smuzhiyun #define TOP_MOUT_ACLK_GSCL_FIMC 50 66*4882a593Smuzhiyun #define TOP_MOUT_GSCL_BUSTOP_FIMC 51 67*4882a593Smuzhiyun #define TOP_MOUT_ACLK_GSCL_333 52 68*4882a593Smuzhiyun #define TOP_MOUT_GSCL_BUSTOP_333 53 69*4882a593Smuzhiyun #define TOP_MOUT_ACLK_GSCL_400 54 70*4882a593Smuzhiyun #define TOP_MOUT_M2M_MEDIATOP_400 55 71*4882a593Smuzhiyun #define TOP_DOUT_ACLK_MFC_333 56 72*4882a593Smuzhiyun #define TOP_DOUT_ACLK_G2D_333 57 73*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 74*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 75*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 76*4882a593Smuzhiyun #define TOP_DOUT_ACLK_GSCL_FIMC 61 77*4882a593Smuzhiyun #define TOP_DOUT_ACLK_GSCL_400 62 78*4882a593Smuzhiyun #define TOP_DOUT_ACLK_GSCL_333 63 79*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SPI0_B 64 80*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SPI0_A 65 81*4882a593Smuzhiyun #define TOP_DOUT_ACLK_ISP1_400 66 82*4882a593Smuzhiyun #define TOP_DOUT_ACLK_ISP1_266 67 83*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_UART 68 84*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SPI1_B 69 85*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SPI1_A 70 86*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 87*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 88*4882a593Smuzhiyun #define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 89*4882a593Smuzhiyun #define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 90*4882a593Smuzhiyun #define TOP_DOUT_SCLK_DISP_PIXEL 75 91*4882a593Smuzhiyun #define TOP_DOUT_ACLK_DISP_222 76 92*4882a593Smuzhiyun #define TOP_DOUT_ACLK_DISP_333 77 93*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS4_100 78 94*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS4_400 79 95*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS3_100 80 96*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS3_400 81 97*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS2_100 82 98*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS2_400 83 99*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS1_100 84 100*4882a593Smuzhiyun #define TOP_DOUT_ACLK_BUS1_400 85 101*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI1_B 86 102*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI1_A 87 103*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI0_B 88 104*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI0_A 89 105*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_UART0 90 106*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_UART2 91 107*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_UART1 92 108*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI2_B 93 109*4882a593Smuzhiyun #define TOP_DOUT_SCLK_PERI_SPI2_A 94 110*4882a593Smuzhiyun #define TOP_DOUT_ACLK_PERI_AUD 95 111*4882a593Smuzhiyun #define TOP_DOUT_ACLK_PERI_66 96 112*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 113*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 114*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 115*4882a593Smuzhiyun #define TOP_DOUT_ACLK_FSYS_200 100 116*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 117*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 118*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 119*4882a593Smuzhiyun #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 120*4882a593Smuzhiyun #define TOP_SCLK_FIMD1 105 121*4882a593Smuzhiyun #define TOP_SCLK_MMC2 106 122*4882a593Smuzhiyun #define TOP_SCLK_MMC1 107 123*4882a593Smuzhiyun #define TOP_SCLK_MMC0 108 124*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 125*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 126*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 127*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 128*4882a593Smuzhiyun #define phyclk_hdmi_phy_tmds_clko 113 129*4882a593Smuzhiyun #define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 130*4882a593Smuzhiyun #define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 131*4882a593Smuzhiyun #define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 132*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 133*4882a593Smuzhiyun #define PHYCLK_DPTX_PHY_CLK_DIV2 118 134*4882a593Smuzhiyun #define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 135*4882a593Smuzhiyun #define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 136*4882a593Smuzhiyun #define PHYCLK_USBHOST20_PHY_FREECLK 121 137*4882a593Smuzhiyun #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 138*4882a593Smuzhiyun #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 139*4882a593Smuzhiyun #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 140*4882a593Smuzhiyun #define TOP_NR_CLK 125 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* List Of Clocks For CMU_EGL */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define EGL_FOUT_EGL_PLL 1 146*4882a593Smuzhiyun #define EGL_FOUT_EGL_DPLL 2 147*4882a593Smuzhiyun #define EGL_MOUT_EGL_B 3 148*4882a593Smuzhiyun #define EGL_MOUT_EGL_PLL 4 149*4882a593Smuzhiyun #define EGL_DOUT_EGL_PLL 5 150*4882a593Smuzhiyun #define EGL_DOUT_EGL_PCLK_DBG 6 151*4882a593Smuzhiyun #define EGL_DOUT_EGL_ATCLK 7 152*4882a593Smuzhiyun #define EGL_DOUT_PCLK_EGL 8 153*4882a593Smuzhiyun #define EGL_DOUT_ACLK_EGL 9 154*4882a593Smuzhiyun #define EGL_DOUT_EGL2 10 155*4882a593Smuzhiyun #define EGL_DOUT_EGL1 11 156*4882a593Smuzhiyun #define EGL_NR_CLK 12 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* List Of Clocks For CMU_KFC */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define KFC_FOUT_KFC_PLL 1 162*4882a593Smuzhiyun #define KFC_MOUT_KFC_PLL 2 163*4882a593Smuzhiyun #define KFC_MOUT_KFC 3 164*4882a593Smuzhiyun #define KFC_DOUT_KFC_PLL 4 165*4882a593Smuzhiyun #define KFC_DOUT_PCLK_KFC 5 166*4882a593Smuzhiyun #define KFC_DOUT_ACLK_KFC 6 167*4882a593Smuzhiyun #define KFC_DOUT_KFC_PCLK_DBG 7 168*4882a593Smuzhiyun #define KFC_DOUT_KFC_ATCLK 8 169*4882a593Smuzhiyun #define KFC_DOUT_KFC2 9 170*4882a593Smuzhiyun #define KFC_DOUT_KFC1 10 171*4882a593Smuzhiyun #define KFC_NR_CLK 11 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* List Of Clocks For CMU_MIF */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define MIF_FOUT_MEM_PLL 1 177*4882a593Smuzhiyun #define MIF_FOUT_MEDIA_PLL 2 178*4882a593Smuzhiyun #define MIF_FOUT_BUS_PLL 3 179*4882a593Smuzhiyun #define MIF_MOUT_CLK2X_PHY 4 180*4882a593Smuzhiyun #define MIF_MOUT_MIF_DREX2X 5 181*4882a593Smuzhiyun #define MIF_MOUT_CLKM_PHY 6 182*4882a593Smuzhiyun #define MIF_MOUT_MIF_DREX 7 183*4882a593Smuzhiyun #define MIF_MOUT_MEDIA_PLL 8 184*4882a593Smuzhiyun #define MIF_MOUT_BUS_PLL 9 185*4882a593Smuzhiyun #define MIF_MOUT_MEM_PLL 10 186*4882a593Smuzhiyun #define MIF_DOUT_ACLK_BUS_100 11 187*4882a593Smuzhiyun #define MIF_DOUT_ACLK_BUS_200 12 188*4882a593Smuzhiyun #define MIF_DOUT_ACLK_MIF_466 13 189*4882a593Smuzhiyun #define MIF_DOUT_CLK2X_PHY 14 190*4882a593Smuzhiyun #define MIF_DOUT_CLKM_PHY 15 191*4882a593Smuzhiyun #define MIF_DOUT_BUS_PLL 16 192*4882a593Smuzhiyun #define MIF_DOUT_MEM_PLL 17 193*4882a593Smuzhiyun #define MIF_DOUT_MEDIA_PLL 18 194*4882a593Smuzhiyun #define MIF_CLK_LPDDR3PHY_WRAP1 19 195*4882a593Smuzhiyun #define MIF_CLK_LPDDR3PHY_WRAP0 20 196*4882a593Smuzhiyun #define MIF_CLK_MONOCNT 21 197*4882a593Smuzhiyun #define MIF_CLK_MIF_RTC 22 198*4882a593Smuzhiyun #define MIF_CLK_DREX1 23 199*4882a593Smuzhiyun #define MIF_CLK_DREX0 24 200*4882a593Smuzhiyun #define MIF_CLK_INTMEM 25 201*4882a593Smuzhiyun #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 202*4882a593Smuzhiyun #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 203*4882a593Smuzhiyun #define MIF_NR_CLK 28 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* List Of Clocks For CMU_G3D */ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define G3D_FOUT_G3D_PLL 1 209*4882a593Smuzhiyun #define G3D_MOUT_G3D_PLL 2 210*4882a593Smuzhiyun #define G3D_DOUT_PCLK_G3D 3 211*4882a593Smuzhiyun #define G3D_DOUT_ACLK_G3D 4 212*4882a593Smuzhiyun #define G3D_CLK_G3D_HPM 5 213*4882a593Smuzhiyun #define G3D_CLK_G3D 6 214*4882a593Smuzhiyun #define G3D_NR_CLK 7 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* List Of Clocks For CMU_AUD */ 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #define AUD_MOUT_SCLK_AUD_PCM 1 220*4882a593Smuzhiyun #define AUD_MOUT_SCLK_AUD_I2S 2 221*4882a593Smuzhiyun #define AUD_MOUT_AUD_PLL_USER 3 222*4882a593Smuzhiyun #define AUD_DOUT_ACLK_AUD_131 4 223*4882a593Smuzhiyun #define AUD_DOUT_SCLK_AUD_UART 5 224*4882a593Smuzhiyun #define AUD_DOUT_SCLK_AUD_PCM 6 225*4882a593Smuzhiyun #define AUD_DOUT_SCLK_AUD_I2S 7 226*4882a593Smuzhiyun #define AUD_CLK_AUD_UART 8 227*4882a593Smuzhiyun #define AUD_CLK_PCM 9 228*4882a593Smuzhiyun #define AUD_CLK_I2S 10 229*4882a593Smuzhiyun #define AUD_CLK_DMAC 11 230*4882a593Smuzhiyun #define AUD_CLK_SRAMC 12 231*4882a593Smuzhiyun #define AUD_SCLK_AUD_UART 13 232*4882a593Smuzhiyun #define AUD_SCLK_PCM 14 233*4882a593Smuzhiyun #define AUD_SCLK_I2S 15 234*4882a593Smuzhiyun #define AUD_NR_CLK 16 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* List Of Clocks For CMU_MFC */ 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define MFC_MOUT_ACLK_MFC_333_USER 1 240*4882a593Smuzhiyun #define MFC_DOUT_PCLK_MFC_83 2 241*4882a593Smuzhiyun #define MFC_CLK_MFC 3 242*4882a593Smuzhiyun #define MFC_CLK_SMMU2_MFCM1 4 243*4882a593Smuzhiyun #define MFC_CLK_SMMU2_MFCM0 5 244*4882a593Smuzhiyun #define MFC_NR_CLK 6 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* List Of Clocks For CMU_GSCL */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define GSCL_MOUT_ACLK_CSIS 1 250*4882a593Smuzhiyun #define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 251*4882a593Smuzhiyun #define GSCL_MOUT_ACLK_M2M_400_USER 3 252*4882a593Smuzhiyun #define GSCL_MOUT_ACLK_GSCL_333_USER 4 253*4882a593Smuzhiyun #define GSCL_DOUT_ACLK_CSIS_200 5 254*4882a593Smuzhiyun #define GSCL_DOUT_PCLK_M2M_100 6 255*4882a593Smuzhiyun #define GSCL_CLK_PIXEL_GSCL1 7 256*4882a593Smuzhiyun #define GSCL_CLK_PIXEL_GSCL0 8 257*4882a593Smuzhiyun #define GSCL_CLK_MSCL1 9 258*4882a593Smuzhiyun #define GSCL_CLK_MSCL0 10 259*4882a593Smuzhiyun #define GSCL_CLK_GSCL1 11 260*4882a593Smuzhiyun #define GSCL_CLK_GSCL0 12 261*4882a593Smuzhiyun #define GSCL_CLK_FIMC_LITE_D 13 262*4882a593Smuzhiyun #define GSCL_CLK_FIMC_LITE_B 14 263*4882a593Smuzhiyun #define GSCL_CLK_FIMC_LITE_A 15 264*4882a593Smuzhiyun #define GSCL_CLK_CSIS1 16 265*4882a593Smuzhiyun #define GSCL_CLK_CSIS0 17 266*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_LITE_D 18 267*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_LITE_B 19 268*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_LITE_A 20 269*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_GSCL0 21 270*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_GSCL1 22 271*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_MSCL0 23 272*4882a593Smuzhiyun #define GSCL_CLK_SMMU3_MSCL1 24 273*4882a593Smuzhiyun #define GSCL_SCLK_CSIS1_WRAP 25 274*4882a593Smuzhiyun #define GSCL_SCLK_CSIS0_WRAP 26 275*4882a593Smuzhiyun #define GSCL_NR_CLK 27 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* List Of Clocks For CMU_FSYS */ 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun #define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 281*4882a593Smuzhiyun #define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 282*4882a593Smuzhiyun #define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 283*4882a593Smuzhiyun #define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 284*4882a593Smuzhiyun #define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 285*4882a593Smuzhiyun #define FSYS_CLK_TSI 6 286*4882a593Smuzhiyun #define FSYS_CLK_USBLINK 7 287*4882a593Smuzhiyun #define FSYS_CLK_USBHOST20 8 288*4882a593Smuzhiyun #define FSYS_CLK_USBDRD30 9 289*4882a593Smuzhiyun #define FSYS_CLK_SROMC 10 290*4882a593Smuzhiyun #define FSYS_CLK_PDMA 11 291*4882a593Smuzhiyun #define FSYS_CLK_MMC2 12 292*4882a593Smuzhiyun #define FSYS_CLK_MMC1 13 293*4882a593Smuzhiyun #define FSYS_CLK_MMC0 14 294*4882a593Smuzhiyun #define FSYS_CLK_RTIC 15 295*4882a593Smuzhiyun #define FSYS_CLK_SMMU_RTIC 16 296*4882a593Smuzhiyun #define FSYS_PHYCLK_USBDRD30 17 297*4882a593Smuzhiyun #define FSYS_PHYCLK_USBHOST20 18 298*4882a593Smuzhiyun #define FSYS_NR_CLK 19 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* List Of Clocks For CMU_PERI */ 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define PERI_MOUT_SCLK_SPDIF 1 304*4882a593Smuzhiyun #define PERI_MOUT_SCLK_I2SCOD 2 305*4882a593Smuzhiyun #define PERI_MOUT_SCLK_PCM 3 306*4882a593Smuzhiyun #define PERI_DOUT_I2S 4 307*4882a593Smuzhiyun #define PERI_DOUT_PCM 5 308*4882a593Smuzhiyun #define PERI_CLK_WDT_KFC 6 309*4882a593Smuzhiyun #define PERI_CLK_WDT_EGL 7 310*4882a593Smuzhiyun #define PERI_CLK_HSIC3 8 311*4882a593Smuzhiyun #define PERI_CLK_HSIC2 9 312*4882a593Smuzhiyun #define PERI_CLK_HSIC1 10 313*4882a593Smuzhiyun #define PERI_CLK_HSIC0 11 314*4882a593Smuzhiyun #define PERI_CLK_PCM 12 315*4882a593Smuzhiyun #define PERI_CLK_MCT 13 316*4882a593Smuzhiyun #define PERI_CLK_I2S 14 317*4882a593Smuzhiyun #define PERI_CLK_I2CHDMI 15 318*4882a593Smuzhiyun #define PERI_CLK_I2C7 16 319*4882a593Smuzhiyun #define PERI_CLK_I2C6 17 320*4882a593Smuzhiyun #define PERI_CLK_I2C5 18 321*4882a593Smuzhiyun #define PERI_CLK_I2C4 19 322*4882a593Smuzhiyun #define PERI_CLK_I2C9 20 323*4882a593Smuzhiyun #define PERI_CLK_I2C8 21 324*4882a593Smuzhiyun #define PERI_CLK_I2C11 22 325*4882a593Smuzhiyun #define PERI_CLK_I2C10 23 326*4882a593Smuzhiyun #define PERI_CLK_HDMICEC 24 327*4882a593Smuzhiyun #define PERI_CLK_EFUSE_WRITER 25 328*4882a593Smuzhiyun #define PERI_CLK_ABB 26 329*4882a593Smuzhiyun #define PERI_CLK_UART2 27 330*4882a593Smuzhiyun #define PERI_CLK_UART1 28 331*4882a593Smuzhiyun #define PERI_CLK_UART0 29 332*4882a593Smuzhiyun #define PERI_CLK_ADC 30 333*4882a593Smuzhiyun #define PERI_CLK_TMU4 31 334*4882a593Smuzhiyun #define PERI_CLK_TMU3 32 335*4882a593Smuzhiyun #define PERI_CLK_TMU2 33 336*4882a593Smuzhiyun #define PERI_CLK_TMU1 34 337*4882a593Smuzhiyun #define PERI_CLK_TMU0 35 338*4882a593Smuzhiyun #define PERI_CLK_SPI2 36 339*4882a593Smuzhiyun #define PERI_CLK_SPI1 37 340*4882a593Smuzhiyun #define PERI_CLK_SPI0 38 341*4882a593Smuzhiyun #define PERI_CLK_SPDIF 39 342*4882a593Smuzhiyun #define PERI_CLK_PWM 40 343*4882a593Smuzhiyun #define PERI_CLK_UART4 41 344*4882a593Smuzhiyun #define PERI_CLK_CHIPID 42 345*4882a593Smuzhiyun #define PERI_CLK_PROVKEY0 43 346*4882a593Smuzhiyun #define PERI_CLK_PROVKEY1 44 347*4882a593Smuzhiyun #define PERI_CLK_SECKEY 45 348*4882a593Smuzhiyun #define PERI_CLK_TOP_RTC 46 349*4882a593Smuzhiyun #define PERI_CLK_TZPC10 47 350*4882a593Smuzhiyun #define PERI_CLK_TZPC9 48 351*4882a593Smuzhiyun #define PERI_CLK_TZPC8 49 352*4882a593Smuzhiyun #define PERI_CLK_TZPC7 50 353*4882a593Smuzhiyun #define PERI_CLK_TZPC6 51 354*4882a593Smuzhiyun #define PERI_CLK_TZPC5 52 355*4882a593Smuzhiyun #define PERI_CLK_TZPC4 53 356*4882a593Smuzhiyun #define PERI_CLK_TZPC3 54 357*4882a593Smuzhiyun #define PERI_CLK_TZPC2 55 358*4882a593Smuzhiyun #define PERI_CLK_TZPC1 56 359*4882a593Smuzhiyun #define PERI_CLK_TZPC0 57 360*4882a593Smuzhiyun #define PERI_SCLK_UART2 58 361*4882a593Smuzhiyun #define PERI_SCLK_UART1 59 362*4882a593Smuzhiyun #define PERI_SCLK_UART0 60 363*4882a593Smuzhiyun #define PERI_SCLK_SPI2 61 364*4882a593Smuzhiyun #define PERI_SCLK_SPI1 62 365*4882a593Smuzhiyun #define PERI_SCLK_SPI0 63 366*4882a593Smuzhiyun #define PERI_SCLK_SPDIF 64 367*4882a593Smuzhiyun #define PERI_SCLK_I2S 65 368*4882a593Smuzhiyun #define PERI_SCLK_PCM1 66 369*4882a593Smuzhiyun #define PERI_NR_CLK 67 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* List Of Clocks For CMU_DISP */ 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define DISP_MOUT_SCLK_HDMI_SPDIF 1 375*4882a593Smuzhiyun #define DISP_MOUT_SCLK_HDMI_PIXEL 2 376*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 377*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 378*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 379*4882a593Smuzhiyun #define DISP_MOUT_HDMI_PHY_PIXEL 6 380*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 381*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 382*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 383*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 384*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 385*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 386*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 387*4882a593Smuzhiyun #define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 388*4882a593Smuzhiyun #define DISP_MOUT_ACLK_DISP_222_USER 15 389*4882a593Smuzhiyun #define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 390*4882a593Smuzhiyun #define DISP_MOUT_ACLK_DISP_333_USER 17 391*4882a593Smuzhiyun #define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 392*4882a593Smuzhiyun #define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 393*4882a593Smuzhiyun #define DISP_DOUT_PCLK_DISP_111 20 394*4882a593Smuzhiyun #define DISP_CLK_SMMU_TV 21 395*4882a593Smuzhiyun #define DISP_CLK_SMMU_FIMD1M1 22 396*4882a593Smuzhiyun #define DISP_CLK_SMMU_FIMD1M0 23 397*4882a593Smuzhiyun #define DISP_CLK_PIXEL_MIXER 24 398*4882a593Smuzhiyun #define DISP_CLK_PIXEL_DISP 25 399*4882a593Smuzhiyun #define DISP_CLK_MIXER 26 400*4882a593Smuzhiyun #define DISP_CLK_MIPIPHY 27 401*4882a593Smuzhiyun #define DISP_CLK_HDMIPHY 28 402*4882a593Smuzhiyun #define DISP_CLK_HDMI 29 403*4882a593Smuzhiyun #define DISP_CLK_FIMD1 30 404*4882a593Smuzhiyun #define DISP_CLK_DSIM1 31 405*4882a593Smuzhiyun #define DISP_CLK_DPPHY 32 406*4882a593Smuzhiyun #define DISP_CLK_DP 33 407*4882a593Smuzhiyun #define DISP_SCLK_PIXEL 34 408*4882a593Smuzhiyun #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 409*4882a593Smuzhiyun #define DISP_NR_CLK 36 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun /* List Of Clocks For CMU_G2D */ 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun #define G2D_MOUT_ACLK_G2D_333_USER 1 415*4882a593Smuzhiyun #define G2D_DOUT_PCLK_G2D_83 2 416*4882a593Smuzhiyun #define G2D_CLK_SMMU3_JPEG 3 417*4882a593Smuzhiyun #define G2D_CLK_MDMA 4 418*4882a593Smuzhiyun #define G2D_CLK_JPEG 5 419*4882a593Smuzhiyun #define G2D_CLK_G2D 6 420*4882a593Smuzhiyun #define G2D_CLK_SSS 7 421*4882a593Smuzhiyun #define G2D_CLK_SLIM_SSS 8 422*4882a593Smuzhiyun #define G2D_CLK_SMMU_SLIM_SSS 9 423*4882a593Smuzhiyun #define G2D_CLK_SMMU_SSS 10 424*4882a593Smuzhiyun #define G2D_CLK_SMMU_MDMA 11 425*4882a593Smuzhiyun #define G2D_CLK_SMMU3_G2D 12 426*4882a593Smuzhiyun #define G2D_NR_CLK 13 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun /* List Of Clocks For CMU_ISP */ 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define ISP_MOUT_ISP_400_USER 1 432*4882a593Smuzhiyun #define ISP_MOUT_ISP_266_USER 2 433*4882a593Smuzhiyun #define ISP_DOUT_SCLK_MPWM 3 434*4882a593Smuzhiyun #define ISP_DOUT_CA5_PCLKDBG 4 435*4882a593Smuzhiyun #define ISP_DOUT_CA5_ATCLKIN 5 436*4882a593Smuzhiyun #define ISP_DOUT_PCLK_ISP_133 6 437*4882a593Smuzhiyun #define ISP_DOUT_PCLK_ISP_66 7 438*4882a593Smuzhiyun #define ISP_CLK_GIC 8 439*4882a593Smuzhiyun #define ISP_CLK_WDT 9 440*4882a593Smuzhiyun #define ISP_CLK_UART 10 441*4882a593Smuzhiyun #define ISP_CLK_SPI1 11 442*4882a593Smuzhiyun #define ISP_CLK_SPI0 12 443*4882a593Smuzhiyun #define ISP_CLK_SMMU_SCALERP 13 444*4882a593Smuzhiyun #define ISP_CLK_SMMU_SCALERC 14 445*4882a593Smuzhiyun #define ISP_CLK_SMMU_ISPCX 15 446*4882a593Smuzhiyun #define ISP_CLK_SMMU_ISP 16 447*4882a593Smuzhiyun #define ISP_CLK_SMMU_FD 17 448*4882a593Smuzhiyun #define ISP_CLK_SMMU_DRC 18 449*4882a593Smuzhiyun #define ISP_CLK_PWM 19 450*4882a593Smuzhiyun #define ISP_CLK_MTCADC 20 451*4882a593Smuzhiyun #define ISP_CLK_MPWM 21 452*4882a593Smuzhiyun #define ISP_CLK_MCUCTL 22 453*4882a593Smuzhiyun #define ISP_CLK_I2C1 23 454*4882a593Smuzhiyun #define ISP_CLK_I2C0 24 455*4882a593Smuzhiyun #define ISP_CLK_FIMC_SCALERP 25 456*4882a593Smuzhiyun #define ISP_CLK_FIMC_SCALERC 26 457*4882a593Smuzhiyun #define ISP_CLK_FIMC 27 458*4882a593Smuzhiyun #define ISP_CLK_FIMC_FD 28 459*4882a593Smuzhiyun #define ISP_CLK_FIMC_DRC 29 460*4882a593Smuzhiyun #define ISP_CLK_CA5 30 461*4882a593Smuzhiyun #define ISP_SCLK_SPI0_EXT 31 462*4882a593Smuzhiyun #define ISP_SCLK_SPI1_EXT 32 463*4882a593Smuzhiyun #define ISP_SCLK_UART_EXT 33 464*4882a593Smuzhiyun #define ISP_NR_CLK 34 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun #endif 467