1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H 3*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_EFM32_CMU_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define clk_HFXO 0 6*4882a593Smuzhiyun #define clk_HFRCO 1 7*4882a593Smuzhiyun #define clk_LFXO 2 8*4882a593Smuzhiyun #define clk_LFRCO 3 9*4882a593Smuzhiyun #define clk_ULFRCO 4 10*4882a593Smuzhiyun #define clk_AUXHFRCO 5 11*4882a593Smuzhiyun #define clk_HFCLKNODIV 6 12*4882a593Smuzhiyun #define clk_HFCLK 7 13*4882a593Smuzhiyun #define clk_HFPERCLK 8 14*4882a593Smuzhiyun #define clk_HFCORECLK 9 15*4882a593Smuzhiyun #define clk_LFACLK 10 16*4882a593Smuzhiyun #define clk_LFBCLK 11 17*4882a593Smuzhiyun #define clk_WDOGCLK 12 18*4882a593Smuzhiyun #define clk_HFCORECLKDMA 13 19*4882a593Smuzhiyun #define clk_HFCORECLKAES 14 20*4882a593Smuzhiyun #define clk_HFCORECLKUSBC 15 21*4882a593Smuzhiyun #define clk_HFCORECLKUSB 16 22*4882a593Smuzhiyun #define clk_HFCORECLKLE 17 23*4882a593Smuzhiyun #define clk_HFCORECLKEBI 18 24*4882a593Smuzhiyun #define clk_HFPERCLKUSART0 19 25*4882a593Smuzhiyun #define clk_HFPERCLKUSART1 20 26*4882a593Smuzhiyun #define clk_HFPERCLKUSART2 21 27*4882a593Smuzhiyun #define clk_HFPERCLKUART0 22 28*4882a593Smuzhiyun #define clk_HFPERCLKUART1 23 29*4882a593Smuzhiyun #define clk_HFPERCLKTIMER0 24 30*4882a593Smuzhiyun #define clk_HFPERCLKTIMER1 25 31*4882a593Smuzhiyun #define clk_HFPERCLKTIMER2 26 32*4882a593Smuzhiyun #define clk_HFPERCLKTIMER3 27 33*4882a593Smuzhiyun #define clk_HFPERCLKACMP0 28 34*4882a593Smuzhiyun #define clk_HFPERCLKACMP1 29 35*4882a593Smuzhiyun #define clk_HFPERCLKI2C0 30 36*4882a593Smuzhiyun #define clk_HFPERCLKI2C1 31 37*4882a593Smuzhiyun #define clk_HFPERCLKGPIO 32 38*4882a593Smuzhiyun #define clk_HFPERCLKVCMP 33 39*4882a593Smuzhiyun #define clk_HFPERCLKPRS 34 40*4882a593Smuzhiyun #define clk_HFPERCLKADC0 35 41*4882a593Smuzhiyun #define clk_HFPERCLKDAC0 36 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */ 44