1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_DRA7_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_DRA7_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define DRA7_CLKCTRL_OFFSET 0x20 9*4882a593Smuzhiyun #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* mpu clocks */ 14*4882a593Smuzhiyun #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* ipu clocks */ 17*4882a593Smuzhiyun #define _DRA7_IPU_CLKCTRL_OFFSET 0x40 18*4882a593Smuzhiyun #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) 19*4882a593Smuzhiyun #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) 20*4882a593Smuzhiyun #define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) 21*4882a593Smuzhiyun #define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) 22*4882a593Smuzhiyun #define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) 23*4882a593Smuzhiyun #define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) 24*4882a593Smuzhiyun #define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) 25*4882a593Smuzhiyun #define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* rtc clocks */ 28*4882a593Smuzhiyun #define DRA7_RTC_CLKCTRL_OFFSET 0x40 29*4882a593Smuzhiyun #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) 30*4882a593Smuzhiyun #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* vip clocks */ 33*4882a593Smuzhiyun #define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 34*4882a593Smuzhiyun #define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 35*4882a593Smuzhiyun #define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* vpe clocks */ 38*4882a593Smuzhiyun #define DRA7_VPE_CLKCTRL_OFFSET 0x60 39*4882a593Smuzhiyun #define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) 40*4882a593Smuzhiyun #define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* coreaon clocks */ 43*4882a593Smuzhiyun #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 44*4882a593Smuzhiyun #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* l3main1 clocks */ 47*4882a593Smuzhiyun #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 48*4882a593Smuzhiyun #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 49*4882a593Smuzhiyun #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 50*4882a593Smuzhiyun #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 51*4882a593Smuzhiyun #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 52*4882a593Smuzhiyun #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 53*4882a593Smuzhiyun #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* dma clocks */ 56*4882a593Smuzhiyun #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* emif clocks */ 59*4882a593Smuzhiyun #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* atl clocks */ 62*4882a593Smuzhiyun #define DRA7_ATL_CLKCTRL_OFFSET 0x0 63*4882a593Smuzhiyun #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) 64*4882a593Smuzhiyun #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* l4cfg clocks */ 67*4882a593Smuzhiyun #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 68*4882a593Smuzhiyun #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 69*4882a593Smuzhiyun #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 70*4882a593Smuzhiyun #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 71*4882a593Smuzhiyun #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 72*4882a593Smuzhiyun #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) 73*4882a593Smuzhiyun #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) 74*4882a593Smuzhiyun #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) 75*4882a593Smuzhiyun #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 76*4882a593Smuzhiyun #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 77*4882a593Smuzhiyun #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 78*4882a593Smuzhiyun #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 79*4882a593Smuzhiyun #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 80*4882a593Smuzhiyun #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) 81*4882a593Smuzhiyun #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* l3instr clocks */ 84*4882a593Smuzhiyun #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 85*4882a593Smuzhiyun #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* dss clocks */ 88*4882a593Smuzhiyun #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 89*4882a593Smuzhiyun #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* gpu clocks */ 92*4882a593Smuzhiyun #define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* l3init clocks */ 95*4882a593Smuzhiyun #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 96*4882a593Smuzhiyun #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 97*4882a593Smuzhiyun #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 98*4882a593Smuzhiyun #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 99*4882a593Smuzhiyun #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 100*4882a593Smuzhiyun #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 101*4882a593Smuzhiyun #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) 102*4882a593Smuzhiyun #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) 103*4882a593Smuzhiyun #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) 104*4882a593Smuzhiyun #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) 105*4882a593Smuzhiyun #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) 106*4882a593Smuzhiyun #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* l4per clocks */ 109*4882a593Smuzhiyun #define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 110*4882a593Smuzhiyun #define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) 111*4882a593Smuzhiyun #define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) 112*4882a593Smuzhiyun #define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) 113*4882a593Smuzhiyun #define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) 114*4882a593Smuzhiyun #define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) 115*4882a593Smuzhiyun #define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) 116*4882a593Smuzhiyun #define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) 117*4882a593Smuzhiyun #define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) 118*4882a593Smuzhiyun #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) 119*4882a593Smuzhiyun #define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) 120*4882a593Smuzhiyun #define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) 121*4882a593Smuzhiyun #define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) 122*4882a593Smuzhiyun #define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) 123*4882a593Smuzhiyun #define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) 124*4882a593Smuzhiyun #define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) 125*4882a593Smuzhiyun #define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) 126*4882a593Smuzhiyun #define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) 127*4882a593Smuzhiyun #define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) 128*4882a593Smuzhiyun #define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) 129*4882a593Smuzhiyun #define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) 130*4882a593Smuzhiyun #define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) 131*4882a593Smuzhiyun #define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) 132*4882a593Smuzhiyun #define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) 133*4882a593Smuzhiyun #define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) 134*4882a593Smuzhiyun #define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) 135*4882a593Smuzhiyun #define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) 136*4882a593Smuzhiyun #define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) 137*4882a593Smuzhiyun #define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) 138*4882a593Smuzhiyun #define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) 139*4882a593Smuzhiyun #define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) 140*4882a593Smuzhiyun #define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) 141*4882a593Smuzhiyun #define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) 142*4882a593Smuzhiyun #define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) 143*4882a593Smuzhiyun #define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) 144*4882a593Smuzhiyun #define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) 145*4882a593Smuzhiyun #define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) 146*4882a593Smuzhiyun #define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) 147*4882a593Smuzhiyun #define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) 148*4882a593Smuzhiyun #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) 149*4882a593Smuzhiyun #define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) 150*4882a593Smuzhiyun #define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) 151*4882a593Smuzhiyun #define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) 152*4882a593Smuzhiyun #define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) 153*4882a593Smuzhiyun #define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) 154*4882a593Smuzhiyun #define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) 155*4882a593Smuzhiyun #define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) 156*4882a593Smuzhiyun #define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) 157*4882a593Smuzhiyun #define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) 158*4882a593Smuzhiyun #define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) 159*4882a593Smuzhiyun #define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) 160*4882a593Smuzhiyun #define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) 161*4882a593Smuzhiyun #define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) 162*4882a593Smuzhiyun #define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) 163*4882a593Smuzhiyun #define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) 164*4882a593Smuzhiyun #define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) 165*4882a593Smuzhiyun #define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) 166*4882a593Smuzhiyun #define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) 167*4882a593Smuzhiyun #define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* wkupaon clocks */ 170*4882a593Smuzhiyun #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 171*4882a593Smuzhiyun #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 172*4882a593Smuzhiyun #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 173*4882a593Smuzhiyun #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 174*4882a593Smuzhiyun #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 175*4882a593Smuzhiyun #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 176*4882a593Smuzhiyun #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 177*4882a593Smuzhiyun #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 178*4882a593Smuzhiyun #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* XXX: Compatibility part end. */ 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* mpu clocks */ 183*4882a593Smuzhiyun #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* dsp1 clocks */ 186*4882a593Smuzhiyun #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* ipu1 clocks */ 189*4882a593Smuzhiyun #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* ipu clocks */ 192*4882a593Smuzhiyun #define DRA7_IPU_CLKCTRL_OFFSET 0x50 193*4882a593Smuzhiyun #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) 194*4882a593Smuzhiyun #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) 195*4882a593Smuzhiyun #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) 196*4882a593Smuzhiyun #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) 197*4882a593Smuzhiyun #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) 198*4882a593Smuzhiyun #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) 199*4882a593Smuzhiyun #define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) 200*4882a593Smuzhiyun #define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* dsp2 clocks */ 203*4882a593Smuzhiyun #define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* rtc clocks */ 206*4882a593Smuzhiyun #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* vip clocks */ 209*4882a593Smuzhiyun #define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 210*4882a593Smuzhiyun #define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 211*4882a593Smuzhiyun #define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* vpe clocks */ 214*4882a593Smuzhiyun #define DRA7_VPE_CLKCTRL_OFFSET 0x60 215*4882a593Smuzhiyun #define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) 216*4882a593Smuzhiyun #define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* coreaon clocks */ 219*4882a593Smuzhiyun #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 220*4882a593Smuzhiyun #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* l3main1 clocks */ 223*4882a593Smuzhiyun #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 224*4882a593Smuzhiyun #define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 225*4882a593Smuzhiyun #define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 226*4882a593Smuzhiyun #define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 227*4882a593Smuzhiyun #define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 228*4882a593Smuzhiyun #define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 229*4882a593Smuzhiyun #define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* ipu2 clocks */ 232*4882a593Smuzhiyun #define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* dma clocks */ 235*4882a593Smuzhiyun #define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* emif clocks */ 238*4882a593Smuzhiyun #define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* atl clocks */ 241*4882a593Smuzhiyun #define DRA7_ATL_CLKCTRL_OFFSET 0x0 242*4882a593Smuzhiyun #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) 243*4882a593Smuzhiyun #define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* l4cfg clocks */ 246*4882a593Smuzhiyun #define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 247*4882a593Smuzhiyun #define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 248*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 249*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 250*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 251*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) 252*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) 253*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) 254*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) 255*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) 256*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 257*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 258*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) 259*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) 260*4882a593Smuzhiyun #define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* l3instr clocks */ 263*4882a593Smuzhiyun #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 264*4882a593Smuzhiyun #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* dss clocks */ 267*4882a593Smuzhiyun #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 268*4882a593Smuzhiyun #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /* l3init clocks */ 271*4882a593Smuzhiyun #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 272*4882a593Smuzhiyun #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 273*4882a593Smuzhiyun #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 274*4882a593Smuzhiyun #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 275*4882a593Smuzhiyun #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 276*4882a593Smuzhiyun #define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 277*4882a593Smuzhiyun #define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) 278*4882a593Smuzhiyun #define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) 279*4882a593Smuzhiyun #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* pcie clocks */ 282*4882a593Smuzhiyun #define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 283*4882a593Smuzhiyun #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) 284*4882a593Smuzhiyun #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) 285*4882a593Smuzhiyun #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* gmac clocks */ 288*4882a593Smuzhiyun #define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 289*4882a593Smuzhiyun #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) 290*4882a593Smuzhiyun #define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* l4per clocks */ 293*4882a593Smuzhiyun #define DRA7_L4PER_CLKCTRL_OFFSET 0x28 294*4882a593Smuzhiyun #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) 295*4882a593Smuzhiyun #define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) 296*4882a593Smuzhiyun #define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) 297*4882a593Smuzhiyun #define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) 298*4882a593Smuzhiyun #define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) 299*4882a593Smuzhiyun #define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) 300*4882a593Smuzhiyun #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) 301*4882a593Smuzhiyun #define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) 302*4882a593Smuzhiyun #define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) 303*4882a593Smuzhiyun #define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) 304*4882a593Smuzhiyun #define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) 305*4882a593Smuzhiyun #define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) 306*4882a593Smuzhiyun #define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) 307*4882a593Smuzhiyun #define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) 308*4882a593Smuzhiyun #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) 309*4882a593Smuzhiyun #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) 310*4882a593Smuzhiyun #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) 311*4882a593Smuzhiyun #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) 312*4882a593Smuzhiyun #define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) 313*4882a593Smuzhiyun #define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) 314*4882a593Smuzhiyun #define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) 315*4882a593Smuzhiyun #define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) 316*4882a593Smuzhiyun #define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) 317*4882a593Smuzhiyun #define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) 318*4882a593Smuzhiyun #define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) 319*4882a593Smuzhiyun #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) 320*4882a593Smuzhiyun #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) 321*4882a593Smuzhiyun #define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) 322*4882a593Smuzhiyun #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) 323*4882a593Smuzhiyun #define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) 324*4882a593Smuzhiyun #define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) 325*4882a593Smuzhiyun #define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* l4sec clocks */ 328*4882a593Smuzhiyun #define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 329*4882a593Smuzhiyun #define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) 330*4882a593Smuzhiyun #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) 331*4882a593Smuzhiyun #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) 332*4882a593Smuzhiyun #define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) 333*4882a593Smuzhiyun #define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) 334*4882a593Smuzhiyun #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) 335*4882a593Smuzhiyun #define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8) 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* l4per2 clocks */ 338*4882a593Smuzhiyun #define DRA7_L4PER2_CLKCTRL_OFFSET 0xc 339*4882a593Smuzhiyun #define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) 340*4882a593Smuzhiyun #define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) 341*4882a593Smuzhiyun #define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) 342*4882a593Smuzhiyun #define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) 343*4882a593Smuzhiyun #define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) 344*4882a593Smuzhiyun #define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) 345*4882a593Smuzhiyun #define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) 346*4882a593Smuzhiyun #define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) 347*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) 348*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) 349*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) 350*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) 351*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) 352*4882a593Smuzhiyun #define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) 353*4882a593Smuzhiyun #define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) 354*4882a593Smuzhiyun #define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) 355*4882a593Smuzhiyun #define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) 356*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) 357*4882a593Smuzhiyun #define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun /* l4per3 clocks */ 360*4882a593Smuzhiyun #define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 361*4882a593Smuzhiyun #define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) 362*4882a593Smuzhiyun #define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) 363*4882a593Smuzhiyun #define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) 364*4882a593Smuzhiyun #define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) 365*4882a593Smuzhiyun #define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) 366*4882a593Smuzhiyun #define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /* wkupaon clocks */ 369*4882a593Smuzhiyun #define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 370*4882a593Smuzhiyun #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 371*4882a593Smuzhiyun #define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) 372*4882a593Smuzhiyun #define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) 373*4882a593Smuzhiyun #define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) 374*4882a593Smuzhiyun #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) 375*4882a593Smuzhiyun #define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) 376*4882a593Smuzhiyun #define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 377*4882a593Smuzhiyun #define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun #endif 380