1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H 3*4882a593Smuzhiyun #define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */ 6*4882a593Smuzhiyun #define GEMINI_NUM_CLKS 20 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define GEMINI_CLK_RTC 0 9*4882a593Smuzhiyun #define GEMINI_CLK_AHB 1 10*4882a593Smuzhiyun #define GEMINI_CLK_APB 2 11*4882a593Smuzhiyun #define GEMINI_CLK_CPU 3 12*4882a593Smuzhiyun #define GEMINI_CLK_PCI 4 13*4882a593Smuzhiyun #define GEMINI_CLK_TVC 5 14*4882a593Smuzhiyun #define GEMINI_CLK_UART 6 15*4882a593Smuzhiyun #define GEMINI_CLK_GATES 7 16*4882a593Smuzhiyun #define GEMINI_CLK_GATE_SECURITY 7 17*4882a593Smuzhiyun #define GEMINI_CLK_GATE_GMAC0 8 18*4882a593Smuzhiyun #define GEMINI_CLK_GATE_GMAC1 9 19*4882a593Smuzhiyun #define GEMINI_CLK_GATE_SATA0 10 20*4882a593Smuzhiyun #define GEMINI_CLK_GATE_SATA1 11 21*4882a593Smuzhiyun #define GEMINI_CLK_GATE_USB0 12 22*4882a593Smuzhiyun #define GEMINI_CLK_GATE_USB1 13 23*4882a593Smuzhiyun #define GEMINI_CLK_GATE_IDE 14 24*4882a593Smuzhiyun #define GEMINI_CLK_GATE_PCI 15 25*4882a593Smuzhiyun #define GEMINI_CLK_GATE_DDR 16 26*4882a593Smuzhiyun #define GEMINI_CLK_GATE_FLASH 17 27*4882a593Smuzhiyun #define GEMINI_CLK_GATE_TVC 18 28*4882a593Smuzhiyun #define GEMINI_CLK_GATE_BOOT 19 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */ 31