1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_CLPS711X_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_CLPS711X_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLPS711X_CLK_DUMMY 0 10*4882a593Smuzhiyun #define CLPS711X_CLK_CPU 1 11*4882a593Smuzhiyun #define CLPS711X_CLK_BUS 2 12*4882a593Smuzhiyun #define CLPS711X_CLK_PLL 3 13*4882a593Smuzhiyun #define CLPS711X_CLK_TIMERREF 4 14*4882a593Smuzhiyun #define CLPS711X_CLK_TIMER1 5 15*4882a593Smuzhiyun #define CLPS711X_CLK_TIMER2 6 16*4882a593Smuzhiyun #define CLPS711X_CLK_PWM 7 17*4882a593Smuzhiyun #define CLPS711X_CLK_SPIREF 8 18*4882a593Smuzhiyun #define CLPS711X_CLK_SPI 9 19*4882a593Smuzhiyun #define CLPS711X_CLK_UART 10 20*4882a593Smuzhiyun #define CLPS711X_CLK_TICK 11 21*4882a593Smuzhiyun #define CLPS711X_CLK_MAX 12 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif 24