1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Baikal-T1 CCU clock indices 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BT1_CCU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CCU_CPU_PLL 0 11*4882a593Smuzhiyun #define CCU_SATA_PLL 1 12*4882a593Smuzhiyun #define CCU_DDR_PLL 2 13*4882a593Smuzhiyun #define CCU_PCIE_PLL 3 14*4882a593Smuzhiyun #define CCU_ETH_PLL 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CCU_AXI_MAIN_CLK 0 17*4882a593Smuzhiyun #define CCU_AXI_DDR_CLK 1 18*4882a593Smuzhiyun #define CCU_AXI_SATA_CLK 2 19*4882a593Smuzhiyun #define CCU_AXI_GMAC0_CLK 3 20*4882a593Smuzhiyun #define CCU_AXI_GMAC1_CLK 4 21*4882a593Smuzhiyun #define CCU_AXI_XGMAC_CLK 5 22*4882a593Smuzhiyun #define CCU_AXI_PCIE_M_CLK 6 23*4882a593Smuzhiyun #define CCU_AXI_PCIE_S_CLK 7 24*4882a593Smuzhiyun #define CCU_AXI_USB_CLK 8 25*4882a593Smuzhiyun #define CCU_AXI_HWA_CLK 9 26*4882a593Smuzhiyun #define CCU_AXI_SRAM_CLK 10 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CCU_SYS_SATA_REF_CLK 0 29*4882a593Smuzhiyun #define CCU_SYS_APB_CLK 1 30*4882a593Smuzhiyun #define CCU_SYS_GMAC0_TX_CLK 2 31*4882a593Smuzhiyun #define CCU_SYS_GMAC0_PTP_CLK 3 32*4882a593Smuzhiyun #define CCU_SYS_GMAC1_TX_CLK 4 33*4882a593Smuzhiyun #define CCU_SYS_GMAC1_PTP_CLK 5 34*4882a593Smuzhiyun #define CCU_SYS_XGMAC_REF_CLK 6 35*4882a593Smuzhiyun #define CCU_SYS_XGMAC_PTP_CLK 7 36*4882a593Smuzhiyun #define CCU_SYS_USB_CLK 8 37*4882a593Smuzhiyun #define CCU_SYS_PVT_CLK 9 38*4882a593Smuzhiyun #define CCU_SYS_HWA_CLK 10 39*4882a593Smuzhiyun #define CCU_SYS_UART_CLK 11 40*4882a593Smuzhiyun #define CCU_SYS_I2C1_CLK 12 41*4882a593Smuzhiyun #define CCU_SYS_I2C2_CLK 13 42*4882a593Smuzhiyun #define CCU_SYS_GPIO_CLK 14 43*4882a593Smuzhiyun #define CCU_SYS_TIMER0_CLK 15 44*4882a593Smuzhiyun #define CCU_SYS_TIMER1_CLK 16 45*4882a593Smuzhiyun #define CCU_SYS_TIMER2_CLK 17 46*4882a593Smuzhiyun #define CCU_SYS_WDT_CLK 18 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ 49