1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree binding constants for Bitmain BM1880 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019 Linaro Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BM1880_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BM1880_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define BM1880_CLK_OSC 0 12*4882a593Smuzhiyun #define BM1880_CLK_MPLL 1 13*4882a593Smuzhiyun #define BM1880_CLK_SPLL 2 14*4882a593Smuzhiyun #define BM1880_CLK_FPLL 3 15*4882a593Smuzhiyun #define BM1880_CLK_DDRPLL 4 16*4882a593Smuzhiyun #define BM1880_CLK_A53 5 17*4882a593Smuzhiyun #define BM1880_CLK_50M_A53 6 18*4882a593Smuzhiyun #define BM1880_CLK_AHB_ROM 7 19*4882a593Smuzhiyun #define BM1880_CLK_AXI_SRAM 8 20*4882a593Smuzhiyun #define BM1880_CLK_DDR_AXI 9 21*4882a593Smuzhiyun #define BM1880_CLK_EFUSE 10 22*4882a593Smuzhiyun #define BM1880_CLK_APB_EFUSE 11 23*4882a593Smuzhiyun #define BM1880_CLK_AXI5_EMMC 12 24*4882a593Smuzhiyun #define BM1880_CLK_EMMC 13 25*4882a593Smuzhiyun #define BM1880_CLK_100K_EMMC 14 26*4882a593Smuzhiyun #define BM1880_CLK_AXI5_SD 15 27*4882a593Smuzhiyun #define BM1880_CLK_SD 16 28*4882a593Smuzhiyun #define BM1880_CLK_100K_SD 17 29*4882a593Smuzhiyun #define BM1880_CLK_500M_ETH0 18 30*4882a593Smuzhiyun #define BM1880_CLK_AXI4_ETH0 19 31*4882a593Smuzhiyun #define BM1880_CLK_500M_ETH1 20 32*4882a593Smuzhiyun #define BM1880_CLK_AXI4_ETH1 21 33*4882a593Smuzhiyun #define BM1880_CLK_AXI1_GDMA 22 34*4882a593Smuzhiyun #define BM1880_CLK_APB_GPIO 23 35*4882a593Smuzhiyun #define BM1880_CLK_APB_GPIO_INTR 24 36*4882a593Smuzhiyun #define BM1880_CLK_GPIO_DB 25 37*4882a593Smuzhiyun #define BM1880_CLK_AXI1_MINER 26 38*4882a593Smuzhiyun #define BM1880_CLK_AHB_SF 27 39*4882a593Smuzhiyun #define BM1880_CLK_SDMA_AXI 28 40*4882a593Smuzhiyun #define BM1880_CLK_SDMA_AUD 29 41*4882a593Smuzhiyun #define BM1880_CLK_APB_I2C 30 42*4882a593Smuzhiyun #define BM1880_CLK_APB_WDT 31 43*4882a593Smuzhiyun #define BM1880_CLK_APB_JPEG 32 44*4882a593Smuzhiyun #define BM1880_CLK_JPEG_AXI 33 45*4882a593Smuzhiyun #define BM1880_CLK_AXI5_NF 34 46*4882a593Smuzhiyun #define BM1880_CLK_APB_NF 35 47*4882a593Smuzhiyun #define BM1880_CLK_NF 36 48*4882a593Smuzhiyun #define BM1880_CLK_APB_PWM 37 49*4882a593Smuzhiyun #define BM1880_CLK_DIV_0_RV 38 50*4882a593Smuzhiyun #define BM1880_CLK_DIV_1_RV 39 51*4882a593Smuzhiyun #define BM1880_CLK_MUX_RV 40 52*4882a593Smuzhiyun #define BM1880_CLK_RV 41 53*4882a593Smuzhiyun #define BM1880_CLK_APB_SPI 42 54*4882a593Smuzhiyun #define BM1880_CLK_TPU_AXI 43 55*4882a593Smuzhiyun #define BM1880_CLK_DIV_UART_500M 44 56*4882a593Smuzhiyun #define BM1880_CLK_UART_500M 45 57*4882a593Smuzhiyun #define BM1880_CLK_APB_UART 46 58*4882a593Smuzhiyun #define BM1880_CLK_APB_I2S 47 59*4882a593Smuzhiyun #define BM1880_CLK_AXI4_USB 48 60*4882a593Smuzhiyun #define BM1880_CLK_APB_USB 49 61*4882a593Smuzhiyun #define BM1880_CLK_125M_USB 50 62*4882a593Smuzhiyun #define BM1880_CLK_33K_USB 51 63*4882a593Smuzhiyun #define BM1880_CLK_DIV_12M_USB 52 64*4882a593Smuzhiyun #define BM1880_CLK_12M_USB 53 65*4882a593Smuzhiyun #define BM1880_CLK_APB_VIDEO 54 66*4882a593Smuzhiyun #define BM1880_CLK_VIDEO_AXI 55 67*4882a593Smuzhiyun #define BM1880_CLK_VPP_AXI 56 68*4882a593Smuzhiyun #define BM1880_CLK_APB_VPP 57 69*4882a593Smuzhiyun #define BM1880_CLK_DIV_0_AXI1 58 70*4882a593Smuzhiyun #define BM1880_CLK_DIV_1_AXI1 59 71*4882a593Smuzhiyun #define BM1880_CLK_AXI1 60 72*4882a593Smuzhiyun #define BM1880_CLK_AXI2 61 73*4882a593Smuzhiyun #define BM1880_CLK_AXI3 62 74*4882a593Smuzhiyun #define BM1880_CLK_AXI4 63 75*4882a593Smuzhiyun #define BM1880_CLK_AXI5 64 76*4882a593Smuzhiyun #define BM1880_CLK_DIV_0_AXI6 65 77*4882a593Smuzhiyun #define BM1880_CLK_DIV_1_AXI6 66 78*4882a593Smuzhiyun #define BM1880_CLK_MUX_AXI6 67 79*4882a593Smuzhiyun #define BM1880_CLK_AXI6 68 80*4882a593Smuzhiyun #define BM1880_NR_CLKS 69 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BM1880_H */ 83