1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM6362_H 4*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM6362_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BCM6362_CLK_ADSL_QPROC 1 7*4882a593Smuzhiyun #define BCM6362_CLK_ADSL_AFE 2 8*4882a593Smuzhiyun #define BCM6362_CLK_ADSL 3 9*4882a593Smuzhiyun #define BCM6362_CLK_MIPS 4 10*4882a593Smuzhiyun #define BCM6362_CLK_WLAN_OCP 5 11*4882a593Smuzhiyun #define BCM6362_CLK_SWPKT_USB 7 12*4882a593Smuzhiyun #define BCM6362_CLK_SWPKT_SAR 8 13*4882a593Smuzhiyun #define BCM6362_CLK_SAR 9 14*4882a593Smuzhiyun #define BCM6362_CLK_ROBOSW 10 15*4882a593Smuzhiyun #define BCM6362_CLK_PCM 11 16*4882a593Smuzhiyun #define BCM6362_CLK_USBD 12 17*4882a593Smuzhiyun #define BCM6362_CLK_USBH 13 18*4882a593Smuzhiyun #define BCM6362_CLK_IPSEC 14 19*4882a593Smuzhiyun #define BCM6362_CLK_SPI 15 20*4882a593Smuzhiyun #define BCM6362_CLK_HSSPI 16 21*4882a593Smuzhiyun #define BCM6362_CLK_PCIE 17 22*4882a593Smuzhiyun #define BCM6362_CLK_FAP 18 23*4882a593Smuzhiyun #define BCM6362_CLK_PHYMIPS 19 24*4882a593Smuzhiyun #define BCM6362_CLK_NAND 20 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ 27