1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM6328_H 4*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM6328_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BCM6328_CLK_PHYMIPS 0 7*4882a593Smuzhiyun #define BCM6328_CLK_ADSL_QPROC 1 8*4882a593Smuzhiyun #define BCM6328_CLK_ADSL_AFE 2 9*4882a593Smuzhiyun #define BCM6328_CLK_ADSL 3 10*4882a593Smuzhiyun #define BCM6328_CLK_MIPS 4 11*4882a593Smuzhiyun #define BCM6328_CLK_SAR 5 12*4882a593Smuzhiyun #define BCM6328_CLK_PCM 6 13*4882a593Smuzhiyun #define BCM6328_CLK_USBD 7 14*4882a593Smuzhiyun #define BCM6328_CLK_USBH 8 15*4882a593Smuzhiyun #define BCM6328_CLK_HSSPI 9 16*4882a593Smuzhiyun #define BCM6328_CLK_PCIE 10 17*4882a593Smuzhiyun #define BCM6328_CLK_ROBOSW 11 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ 20