1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM63268_H 4*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM63268_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BCM63268_CLK_DIS_GLESS 0 7*4882a593Smuzhiyun #define BCM63268_CLK_VDSL_QPROC 1 8*4882a593Smuzhiyun #define BCM63268_CLK_VDSL_AFE 2 9*4882a593Smuzhiyun #define BCM63268_CLK_VDSL 3 10*4882a593Smuzhiyun #define BCM63268_CLK_MIPS 4 11*4882a593Smuzhiyun #define BCM63268_CLK_WLAN_OCP 5 12*4882a593Smuzhiyun #define BCM63268_CLK_DECT 6 13*4882a593Smuzhiyun #define BCM63268_CLK_FAP0 7 14*4882a593Smuzhiyun #define BCM63268_CLK_FAP1 8 15*4882a593Smuzhiyun #define BCM63268_CLK_SAR 9 16*4882a593Smuzhiyun #define BCM63268_CLK_ROBOSW 10 17*4882a593Smuzhiyun #define BCM63268_CLK_PCM 11 18*4882a593Smuzhiyun #define BCM63268_CLK_USBD 12 19*4882a593Smuzhiyun #define BCM63268_CLK_USBH 13 20*4882a593Smuzhiyun #define BCM63268_CLK_IPSEC 14 21*4882a593Smuzhiyun #define BCM63268_CLK_SPI 15 22*4882a593Smuzhiyun #define BCM63268_CLK_HSSPI 16 23*4882a593Smuzhiyun #define BCM63268_CLK_PCIE 17 24*4882a593Smuzhiyun #define BCM63268_CLK_PHYMIPS 18 25*4882a593Smuzhiyun #define BCM63268_CLK_GMAC 19 26*4882a593Smuzhiyun #define BCM63268_CLK_NAND 20 27*4882a593Smuzhiyun #define BCM63268_CLK_TBUS 27 28*4882a593Smuzhiyun #define BCM63268_CLK_ROBOSW250 31 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ 31