1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM6318_H 4*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM6318_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BCM6318_CLK_ADSL_ASB 0 7*4882a593Smuzhiyun #define BCM6318_CLK_USB_ASB 1 8*4882a593Smuzhiyun #define BCM6318_CLK_MIPS_ASB 2 9*4882a593Smuzhiyun #define BCM6318_CLK_PCIE_ASB 3 10*4882a593Smuzhiyun #define BCM6318_CLK_PHYMIPS_ASB 4 11*4882a593Smuzhiyun #define BCM6318_CLK_ROBOSW_ASB 5 12*4882a593Smuzhiyun #define BCM6318_CLK_SAR_ASB 6 13*4882a593Smuzhiyun #define BCM6318_CLK_SDR_ASB 7 14*4882a593Smuzhiyun #define BCM6318_CLK_SWREG_ASB 8 15*4882a593Smuzhiyun #define BCM6318_CLK_PERIPH_ASB 9 16*4882a593Smuzhiyun #define BCM6318_CLK_CPUBUS160 10 17*4882a593Smuzhiyun #define BCM6318_CLK_ADSL 11 18*4882a593Smuzhiyun #define BCM6318_CLK_SAR125 12 19*4882a593Smuzhiyun #define BCM6318_CLK_MIPS 13 20*4882a593Smuzhiyun #define BCM6318_CLK_PCIE 14 21*4882a593Smuzhiyun #define BCM6318_CLK_ROBOSW250 16 22*4882a593Smuzhiyun #define BCM6318_CLK_ROBOSW025 17 23*4882a593Smuzhiyun #define BCM6318_CLK_SDR 19 24*4882a593Smuzhiyun #define BCM6318_CLK_USBD 20 25*4882a593Smuzhiyun #define BCM6318_CLK_HSSPI 25 26*4882a593Smuzhiyun #define BCM6318_CLK_PCIE25 27 27*4882a593Smuzhiyun #define BCM6318_CLK_PHYMIPS 28 28*4882a593Smuzhiyun #define BCM6318_CLK_AFE 29 29*4882a593Smuzhiyun #define BCM6318_CLK_QPROC 30 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define BCM6318_UCLK_ADSL 0 32*4882a593Smuzhiyun #define BCM6318_UCLK_ARB 1 33*4882a593Smuzhiyun #define BCM6318_UCLK_MIPS 2 34*4882a593Smuzhiyun #define BCM6318_UCLK_PCIE 3 35*4882a593Smuzhiyun #define BCM6318_UCLK_PERIPH 4 36*4882a593Smuzhiyun #define BCM6318_UCLK_PHYMIPS 5 37*4882a593Smuzhiyun #define BCM6318_UCLK_ROBOSW 6 38*4882a593Smuzhiyun #define BCM6318_UCLK_SAR 7 39*4882a593Smuzhiyun #define BCM6318_UCLK_SDR 8 40*4882a593Smuzhiyun #define BCM6318_UCLK_USB 9 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ 43