1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_BCM3368_H 4*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_BCM3368_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BCM3368_CLK_MAC 3 7*4882a593Smuzhiyun #define BCM3368_CLK_TC 5 8*4882a593Smuzhiyun #define BCM3368_CLK_US_TOP 6 9*4882a593Smuzhiyun #define BCM3368_CLK_DS_TOP 7 10*4882a593Smuzhiyun #define BCM3368_CLK_ACM 8 11*4882a593Smuzhiyun #define BCM3368_CLK_SPI 9 12*4882a593Smuzhiyun #define BCM3368_CLK_USBS 10 13*4882a593Smuzhiyun #define BCM3368_CLK_BMU 11 14*4882a593Smuzhiyun #define BCM3368_CLK_PCM 12 15*4882a593Smuzhiyun #define BCM3368_CLK_NTP 13 16*4882a593Smuzhiyun #define BCM3368_CLK_ACP_B 14 17*4882a593Smuzhiyun #define BCM3368_CLK_ACP_A 15 18*4882a593Smuzhiyun #define BCM3368_CLK_EMUSB 17 19*4882a593Smuzhiyun #define BCM3368_CLK_ENET0 18 20*4882a593Smuzhiyun #define BCM3368_CLK_ENET1 19 21*4882a593Smuzhiyun #define BCM3368_CLK_USBSU 20 22*4882a593Smuzhiyun #define BCM3368_CLK_EPHY 21 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_BCM3368_H */ 25