xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/bcm2835.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2015 Broadcom Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #define BCM2835_PLLA			0
7*4882a593Smuzhiyun #define BCM2835_PLLB			1
8*4882a593Smuzhiyun #define BCM2835_PLLC			2
9*4882a593Smuzhiyun #define BCM2835_PLLD			3
10*4882a593Smuzhiyun #define BCM2835_PLLH			4
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define BCM2835_PLLA_CORE		5
13*4882a593Smuzhiyun #define BCM2835_PLLA_PER		6
14*4882a593Smuzhiyun #define BCM2835_PLLB_ARM		7
15*4882a593Smuzhiyun #define BCM2835_PLLC_CORE0		8
16*4882a593Smuzhiyun #define BCM2835_PLLC_CORE1		9
17*4882a593Smuzhiyun #define BCM2835_PLLC_CORE2		10
18*4882a593Smuzhiyun #define BCM2835_PLLC_PER		11
19*4882a593Smuzhiyun #define BCM2835_PLLD_CORE		12
20*4882a593Smuzhiyun #define BCM2835_PLLD_PER		13
21*4882a593Smuzhiyun #define BCM2835_PLLH_RCAL		14
22*4882a593Smuzhiyun #define BCM2835_PLLH_AUX		15
23*4882a593Smuzhiyun #define BCM2835_PLLH_PIX		16
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define BCM2835_CLOCK_TIMER		17
26*4882a593Smuzhiyun #define BCM2835_CLOCK_OTP		18
27*4882a593Smuzhiyun #define BCM2835_CLOCK_UART		19
28*4882a593Smuzhiyun #define BCM2835_CLOCK_VPU		20
29*4882a593Smuzhiyun #define BCM2835_CLOCK_V3D		21
30*4882a593Smuzhiyun #define BCM2835_CLOCK_ISP		22
31*4882a593Smuzhiyun #define BCM2835_CLOCK_H264		23
32*4882a593Smuzhiyun #define BCM2835_CLOCK_VEC		24
33*4882a593Smuzhiyun #define BCM2835_CLOCK_HSM		25
34*4882a593Smuzhiyun #define BCM2835_CLOCK_SDRAM		26
35*4882a593Smuzhiyun #define BCM2835_CLOCK_TSENS		27
36*4882a593Smuzhiyun #define BCM2835_CLOCK_EMMC		28
37*4882a593Smuzhiyun #define BCM2835_CLOCK_PERI_IMAGE	29
38*4882a593Smuzhiyun #define BCM2835_CLOCK_PWM		30
39*4882a593Smuzhiyun #define BCM2835_CLOCK_PCM		31
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define BCM2835_PLLA_DSI0		32
42*4882a593Smuzhiyun #define BCM2835_PLLA_CCP2		33
43*4882a593Smuzhiyun #define BCM2835_PLLD_DSI0		34
44*4882a593Smuzhiyun #define BCM2835_PLLD_DSI1		35
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define BCM2835_CLOCK_AVEO		36
47*4882a593Smuzhiyun #define BCM2835_CLOCK_DFT		37
48*4882a593Smuzhiyun #define BCM2835_CLOCK_GP0		38
49*4882a593Smuzhiyun #define BCM2835_CLOCK_GP1		39
50*4882a593Smuzhiyun #define BCM2835_CLOCK_GP2		40
51*4882a593Smuzhiyun #define BCM2835_CLOCK_SLIM		41
52*4882a593Smuzhiyun #define BCM2835_CLOCK_SMI		42
53*4882a593Smuzhiyun #define BCM2835_CLOCK_TEC		43
54*4882a593Smuzhiyun #define BCM2835_CLOCK_DPI		44
55*4882a593Smuzhiyun #define BCM2835_CLOCK_CAM0		45
56*4882a593Smuzhiyun #define BCM2835_CLOCK_CAM1		46
57*4882a593Smuzhiyun #define BCM2835_CLOCK_DSI0E		47
58*4882a593Smuzhiyun #define BCM2835_CLOCK_DSI1E		48
59*4882a593Smuzhiyun #define BCM2835_CLOCK_DSI0P		49
60*4882a593Smuzhiyun #define BCM2835_CLOCK_DSI1P		50
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define BCM2711_CLOCK_EMMC2		51
63