1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Broadcom Corporation 3*4882a593Smuzhiyun * Copyright 2013 Linaro Limited 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 6*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 11*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _CLOCK_BCM21664_H 16*4882a593Smuzhiyun #define _CLOCK_BCM21664_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * This file defines the values used to specify clocks provided by 20*4882a593Smuzhiyun * the clock control units (CCUs) on Broadcom BCM21664 family SoCs. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* bcm21664 CCU device tree "compatible" strings */ 24*4882a593Smuzhiyun #define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu" 25*4882a593Smuzhiyun #define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu" 26*4882a593Smuzhiyun #define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu" 27*4882a593Smuzhiyun #define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* root CCU clock ids */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define BCM21664_ROOT_CCU_FRAC_1M 0 32*4882a593Smuzhiyun #define BCM21664_ROOT_CCU_CLOCK_COUNT 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* aon CCU clock ids */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BCM21664_AON_CCU_HUB_TIMER 0 37*4882a593Smuzhiyun #define BCM21664_AON_CCU_CLOCK_COUNT 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* master CCU clock ids */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO1 0 42*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO2 1 43*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO3 2 44*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO4 3 45*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO1_SLEEP 4 46*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO2_SLEEP 5 47*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO3_SLEEP 6 48*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_SDIO4_SLEEP 7 49*4882a593Smuzhiyun #define BCM21664_MASTER_CCU_CLOCK_COUNT 8 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* slave CCU clock ids */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_UARTB 0 54*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_UARTB2 1 55*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_UARTB3 2 56*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_BSC1 3 57*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_BSC2 4 58*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_BSC3 5 59*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_BSC4 6 60*4882a593Smuzhiyun #define BCM21664_SLAVE_CCU_CLOCK_COUNT 7 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* _CLOCK_BCM21664_H */ 63