1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * BSD LICENSE 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright(c) 2017 Broadcom. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 8*4882a593Smuzhiyun * are met: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 12*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 13*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in 14*4882a593Smuzhiyun * the documentation and/or other materials provided with the 15*4882a593Smuzhiyun * distribution. 16*4882a593Smuzhiyun * * Neither the name of Broadcom Corporation nor the names of its 17*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived 18*4882a593Smuzhiyun * from this software without specific prior written permission. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #ifndef _CLOCK_BCM_SR_H 34*4882a593Smuzhiyun #define _CLOCK_BCM_SR_H 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ 37*4882a593Smuzhiyun #define BCM_SR_GENPLL0 0 38*4882a593Smuzhiyun #define BCM_SR_GENPLL0_125M_CLK 1 39*4882a593Smuzhiyun #define BCM_SR_GENPLL0_SCR_CLK 2 40*4882a593Smuzhiyun #define BCM_SR_GENPLL0_250M_CLK 3 41*4882a593Smuzhiyun #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 42*4882a593Smuzhiyun #define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5 43*4882a593Smuzhiyun #define BCM_SR_GENPLL0_PAXC_AXI_CLK 6 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* GENPLL 1 clock channel ID MHB PCIE NITRO */ 46*4882a593Smuzhiyun #define BCM_SR_GENPLL1 0 47*4882a593Smuzhiyun #define BCM_SR_GENPLL1_PCIE_TL_CLK 1 48*4882a593Smuzhiyun #define BCM_SR_GENPLL1_MHB_APB_CLK 2 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* GENPLL 2 clock channel ID NITRO MHB*/ 51*4882a593Smuzhiyun #define BCM_SR_GENPLL2 0 52*4882a593Smuzhiyun #define BCM_SR_GENPLL2_NIC_CLK 1 53*4882a593Smuzhiyun #define BCM_SR_GENPLL2_TS_500_CLK 2 54*4882a593Smuzhiyun #define BCM_SR_GENPLL2_125_NITRO_CLK 3 55*4882a593Smuzhiyun #define BCM_SR_GENPLL2_CHIMP_CLK 4 56*4882a593Smuzhiyun #define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 57*4882a593Smuzhiyun #define BCM_SR_GENPLL2_FS4_CLK 6 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* GENPLL 3 HSLS clock channel ID */ 60*4882a593Smuzhiyun #define BCM_SR_GENPLL3 0 61*4882a593Smuzhiyun #define BCM_SR_GENPLL3_HSLS_CLK 1 62*4882a593Smuzhiyun #define BCM_SR_GENPLL3_SDIO_CLK 2 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* GENPLL 4 SCR clock channel ID */ 65*4882a593Smuzhiyun #define BCM_SR_GENPLL4 0 66*4882a593Smuzhiyun #define BCM_SR_GENPLL4_CCN_CLK 1 67*4882a593Smuzhiyun #define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 68*4882a593Smuzhiyun #define BCM_SR_GENPLL4_NOC_CLK 3 69*4882a593Smuzhiyun #define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 70*4882a593Smuzhiyun #define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* GENPLL 5 FS4 clock channel ID */ 73*4882a593Smuzhiyun #define BCM_SR_GENPLL5 0 74*4882a593Smuzhiyun #define BCM_SR_GENPLL5_FS4_HF_CLK 1 75*4882a593Smuzhiyun #define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 76*4882a593Smuzhiyun #define BCM_SR_GENPLL5_RAID_AE_CLK 3 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* GENPLL 6 NITRO clock channel ID */ 79*4882a593Smuzhiyun #define BCM_SR_GENPLL6 0 80*4882a593Smuzhiyun #define BCM_SR_GENPLL6_48_USB_CLK 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* LCPLL0 clock channel ID */ 83*4882a593Smuzhiyun #define BCM_SR_LCPLL0 0 84*4882a593Smuzhiyun #define BCM_SR_LCPLL0_SATA_REFP_CLK 1 85*4882a593Smuzhiyun #define BCM_SR_LCPLL0_SATA_REFN_CLK 2 86*4882a593Smuzhiyun #define BCM_SR_LCPLL0_SATA_350_CLK 3 87*4882a593Smuzhiyun #define BCM_SR_LCPLL0_SATA_500_CLK 4 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* LCPLL1 clock channel ID */ 90*4882a593Smuzhiyun #define BCM_SR_LCPLL1 0 91*4882a593Smuzhiyun #define BCM_SR_LCPLL1_WAN_CLK 1 92*4882a593Smuzhiyun #define BCM_SR_LCPLL1_USB_REF_CLK 2 93*4882a593Smuzhiyun #define BCM_SR_LCPLL1_CRMU_TS_CLK 3 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* LCPLL PCIE clock channel ID */ 96*4882a593Smuzhiyun #define BCM_SR_LCPLL_PCIE 0 97*4882a593Smuzhiyun #define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* GENPLL EMEM0 clock channel ID */ 100*4882a593Smuzhiyun #define BCM_SR_EMEMPLL0 0 101*4882a593Smuzhiyun #define BCM_SR_EMEMPLL0_EMEM_CLK 1 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* GENPLL EMEM0 clock channel ID */ 104*4882a593Smuzhiyun #define BCM_SR_EMEMPLL1 0 105*4882a593Smuzhiyun #define BCM_SR_EMEMPLL1_EMEM_CLK 1 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* GENPLL EMEM0 clock channel ID */ 108*4882a593Smuzhiyun #define BCM_SR_EMEMPLL2 0 109*4882a593Smuzhiyun #define BCM_SR_EMEMPLL2_EMEM_CLK 1 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* _CLOCK_BCM_SR_H */ 112