1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Meson-AXG clock tree IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __AXG_CLKC_H 9*4882a593Smuzhiyun #define __AXG_CLKC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLKID_SYS_PLL 0 12*4882a593Smuzhiyun #define CLKID_FIXED_PLL 1 13*4882a593Smuzhiyun #define CLKID_FCLK_DIV2 2 14*4882a593Smuzhiyun #define CLKID_FCLK_DIV3 3 15*4882a593Smuzhiyun #define CLKID_FCLK_DIV4 4 16*4882a593Smuzhiyun #define CLKID_FCLK_DIV5 5 17*4882a593Smuzhiyun #define CLKID_FCLK_DIV7 6 18*4882a593Smuzhiyun #define CLKID_GP0_PLL 7 19*4882a593Smuzhiyun #define CLKID_CLK81 10 20*4882a593Smuzhiyun #define CLKID_MPLL0 11 21*4882a593Smuzhiyun #define CLKID_MPLL1 12 22*4882a593Smuzhiyun #define CLKID_MPLL2 13 23*4882a593Smuzhiyun #define CLKID_MPLL3 14 24*4882a593Smuzhiyun #define CLKID_DDR 15 25*4882a593Smuzhiyun #define CLKID_AUDIO_LOCKER 16 26*4882a593Smuzhiyun #define CLKID_MIPI_DSI_HOST 17 27*4882a593Smuzhiyun #define CLKID_ISA 18 28*4882a593Smuzhiyun #define CLKID_PL301 19 29*4882a593Smuzhiyun #define CLKID_PERIPHS 20 30*4882a593Smuzhiyun #define CLKID_SPICC0 21 31*4882a593Smuzhiyun #define CLKID_I2C 22 32*4882a593Smuzhiyun #define CLKID_RNG0 23 33*4882a593Smuzhiyun #define CLKID_UART0 24 34*4882a593Smuzhiyun #define CLKID_MIPI_DSI_PHY 25 35*4882a593Smuzhiyun #define CLKID_SPICC1 26 36*4882a593Smuzhiyun #define CLKID_PCIE_A 27 37*4882a593Smuzhiyun #define CLKID_PCIE_B 28 38*4882a593Smuzhiyun #define CLKID_HIU_IFACE 29 39*4882a593Smuzhiyun #define CLKID_ASSIST_MISC 30 40*4882a593Smuzhiyun #define CLKID_SD_EMMC_B 31 41*4882a593Smuzhiyun #define CLKID_SD_EMMC_C 32 42*4882a593Smuzhiyun #define CLKID_DMA 33 43*4882a593Smuzhiyun #define CLKID_SPI 34 44*4882a593Smuzhiyun #define CLKID_AUDIO 35 45*4882a593Smuzhiyun #define CLKID_ETH 36 46*4882a593Smuzhiyun #define CLKID_UART1 37 47*4882a593Smuzhiyun #define CLKID_G2D 38 48*4882a593Smuzhiyun #define CLKID_USB0 39 49*4882a593Smuzhiyun #define CLKID_USB1 40 50*4882a593Smuzhiyun #define CLKID_RESET 41 51*4882a593Smuzhiyun #define CLKID_USB 42 52*4882a593Smuzhiyun #define CLKID_AHB_ARB0 43 53*4882a593Smuzhiyun #define CLKID_EFUSE 44 54*4882a593Smuzhiyun #define CLKID_BOOT_ROM 45 55*4882a593Smuzhiyun #define CLKID_AHB_DATA_BUS 46 56*4882a593Smuzhiyun #define CLKID_AHB_CTRL_BUS 47 57*4882a593Smuzhiyun #define CLKID_USB1_DDR_BRIDGE 48 58*4882a593Smuzhiyun #define CLKID_USB0_DDR_BRIDGE 49 59*4882a593Smuzhiyun #define CLKID_MMC_PCLK 50 60*4882a593Smuzhiyun #define CLKID_VPU_INTR 51 61*4882a593Smuzhiyun #define CLKID_SEC_AHB_AHB3_BRIDGE 52 62*4882a593Smuzhiyun #define CLKID_GIC 53 63*4882a593Smuzhiyun #define CLKID_AO_MEDIA_CPU 54 64*4882a593Smuzhiyun #define CLKID_AO_AHB_SRAM 55 65*4882a593Smuzhiyun #define CLKID_AO_AHB_BUS 56 66*4882a593Smuzhiyun #define CLKID_AO_IFACE 57 67*4882a593Smuzhiyun #define CLKID_AO_I2C 58 68*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0 59 69*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0 60 70*4882a593Smuzhiyun #define CLKID_HIFI_PLL 69 71*4882a593Smuzhiyun #define CLKID_PCIE_CML_EN0 79 72*4882a593Smuzhiyun #define CLKID_PCIE_CML_EN1 80 73*4882a593Smuzhiyun #define CLKID_MIPI_ENABLE 81 74*4882a593Smuzhiyun #define CLKID_GEN_CLK 84 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __AXG_CLKC_H */ 77