xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/axg-audio-clkc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2018 Baylibre SAS.
4*4882a593Smuzhiyun  * Author: Jerome Brunet <jbrunet@baylibre.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __AXG_AUDIO_CLKC_BINDINGS_H
8*4882a593Smuzhiyun #define __AXG_AUDIO_CLKC_BINDINGS_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define AUD_CLKID_DDR_ARB		29
11*4882a593Smuzhiyun #define AUD_CLKID_PDM			30
12*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A		31
13*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B		32
14*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C		33
15*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB		34
16*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A		35
17*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B		36
18*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C		37
19*4882a593Smuzhiyun #define AUD_CLKID_FRDDR_A		38
20*4882a593Smuzhiyun #define AUD_CLKID_FRDDR_B		39
21*4882a593Smuzhiyun #define AUD_CLKID_FRDDR_C		40
22*4882a593Smuzhiyun #define AUD_CLKID_TODDR_A		41
23*4882a593Smuzhiyun #define AUD_CLKID_TODDR_B		42
24*4882a593Smuzhiyun #define AUD_CLKID_TODDR_C		43
25*4882a593Smuzhiyun #define AUD_CLKID_LOOPBACK		44
26*4882a593Smuzhiyun #define AUD_CLKID_SPDIFIN		45
27*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT		46
28*4882a593Smuzhiyun #define AUD_CLKID_RESAMPLE		47
29*4882a593Smuzhiyun #define AUD_CLKID_POWER_DETECT		48
30*4882a593Smuzhiyun #define AUD_CLKID_MST_A_MCLK		49
31*4882a593Smuzhiyun #define AUD_CLKID_MST_B_MCLK		50
32*4882a593Smuzhiyun #define AUD_CLKID_MST_C_MCLK		51
33*4882a593Smuzhiyun #define AUD_CLKID_MST_D_MCLK		52
34*4882a593Smuzhiyun #define AUD_CLKID_MST_E_MCLK		53
35*4882a593Smuzhiyun #define AUD_CLKID_MST_F_MCLK		54
36*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_CLK		55
37*4882a593Smuzhiyun #define AUD_CLKID_SPDIFIN_CLK		56
38*4882a593Smuzhiyun #define AUD_CLKID_PDM_DCLK		57
39*4882a593Smuzhiyun #define AUD_CLKID_PDM_SYSCLK		58
40*4882a593Smuzhiyun #define AUD_CLKID_MST_A_SCLK		79
41*4882a593Smuzhiyun #define AUD_CLKID_MST_B_SCLK		80
42*4882a593Smuzhiyun #define AUD_CLKID_MST_C_SCLK		81
43*4882a593Smuzhiyun #define AUD_CLKID_MST_D_SCLK		82
44*4882a593Smuzhiyun #define AUD_CLKID_MST_E_SCLK		83
45*4882a593Smuzhiyun #define AUD_CLKID_MST_F_SCLK		84
46*4882a593Smuzhiyun #define AUD_CLKID_MST_A_LRCLK		86
47*4882a593Smuzhiyun #define AUD_CLKID_MST_B_LRCLK		87
48*4882a593Smuzhiyun #define AUD_CLKID_MST_C_LRCLK		88
49*4882a593Smuzhiyun #define AUD_CLKID_MST_D_LRCLK		89
50*4882a593Smuzhiyun #define AUD_CLKID_MST_E_LRCLK		90
51*4882a593Smuzhiyun #define AUD_CLKID_MST_F_LRCLK		91
52*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A_SCLK_SEL	116
53*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B_SCLK_SEL	117
54*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C_SCLK_SEL	118
55*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
56*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
57*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
58*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
59*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A_SCLK		123
60*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B_SCLK		124
61*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C_SCLK		125
62*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB_SCLK		126
63*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A_SCLK		127
64*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B_SCLK		128
65*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C_SCLK		129
66*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_A_LRCLK		130
67*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_B_LRCLK		131
68*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_C_LRCLK		132
69*4882a593Smuzhiyun #define AUD_CLKID_TDMIN_LB_LRCLK	133
70*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_A_LRCLK	134
71*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_B_LRCLK	135
72*4882a593Smuzhiyun #define AUD_CLKID_TDMOUT_C_LRCLK	136
73*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_B		151
74*4882a593Smuzhiyun #define AUD_CLKID_SPDIFOUT_B_CLK	152
75*4882a593Smuzhiyun #define AUD_CLKID_TDM_MCLK_PAD0		155
76*4882a593Smuzhiyun #define AUD_CLKID_TDM_MCLK_PAD1		156
77*4882a593Smuzhiyun #define AUD_CLKID_TDM_LRCLK_PAD0	157
78*4882a593Smuzhiyun #define AUD_CLKID_TDM_LRCLK_PAD1	158
79*4882a593Smuzhiyun #define AUD_CLKID_TDM_LRCLK_PAD2	159
80*4882a593Smuzhiyun #define AUD_CLKID_TDM_SCLK_PAD0		160
81*4882a593Smuzhiyun #define AUD_CLKID_TDM_SCLK_PAD1		161
82*4882a593Smuzhiyun #define AUD_CLKID_TDM_SCLK_PAD2		162
83*4882a593Smuzhiyun #define AUD_CLKID_TOP			163
84*4882a593Smuzhiyun #define AUD_CLKID_TORAM			164
85*4882a593Smuzhiyun #define AUD_CLKID_EQDRC			165
86*4882a593Smuzhiyun #define AUD_CLKID_RESAMPLE_B		166
87*4882a593Smuzhiyun #define AUD_CLKID_TOVAD			167
88*4882a593Smuzhiyun #define AUD_CLKID_LOCKER		168
89*4882a593Smuzhiyun #define AUD_CLKID_SPDIFIN_LB		169
90*4882a593Smuzhiyun #define AUD_CLKID_FRDDR_D		170
91*4882a593Smuzhiyun #define AUD_CLKID_TODDR_D		171
92*4882a593Smuzhiyun #define AUD_CLKID_LOOPBACK_B		172
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
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