1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_ATH79_CLK_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_ATH79_CLK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ATH79_CLK_CPU 0 10*4882a593Smuzhiyun #define ATH79_CLK_DDR 1 11*4882a593Smuzhiyun #define ATH79_CLK_AHB 2 12*4882a593Smuzhiyun #define ATH79_CLK_REF 3 13*4882a593Smuzhiyun #define ATH79_CLK_MDIO 4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ATH79_CLK_END 5 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #endif /* __DT_BINDINGS_ATH79_CLK_H */ 18