1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for AT91 pmc status. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The constants defined in this header are being used in dts. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_AT91_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_AT91_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PMC_TYPE_CORE 0 12*4882a593Smuzhiyun #define PMC_TYPE_SYSTEM 1 13*4882a593Smuzhiyun #define PMC_TYPE_PERIPHERAL 2 14*4882a593Smuzhiyun #define PMC_TYPE_GCK 3 15*4882a593Smuzhiyun #define PMC_TYPE_PROGRAMMABLE 4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define PMC_SLOW 0 18*4882a593Smuzhiyun #define PMC_MCK 1 19*4882a593Smuzhiyun #define PMC_UTMI 2 20*4882a593Smuzhiyun #define PMC_MAIN 3 21*4882a593Smuzhiyun #define PMC_MCK2 4 22*4882a593Smuzhiyun #define PMC_I2S0_MUX 5 23*4882a593Smuzhiyun #define PMC_I2S1_MUX 6 24*4882a593Smuzhiyun #define PMC_PLLACK 7 25*4882a593Smuzhiyun #define PMC_PLLBCK 8 26*4882a593Smuzhiyun #define PMC_AUDIOPLLCK 9 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifndef AT91_PMC_MOSCS 29*4882a593Smuzhiyun #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ 30*4882a593Smuzhiyun #define AT91_PMC_LOCKA 1 /* PLLA Lock */ 31*4882a593Smuzhiyun #define AT91_PMC_LOCKB 2 /* PLLB Lock */ 32*4882a593Smuzhiyun #define AT91_PMC_MCKRDY 3 /* Master Clock */ 33*4882a593Smuzhiyun #define AT91_PMC_LOCKU 6 /* UPLL Lock */ 34*4882a593Smuzhiyun #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ 35*4882a593Smuzhiyun #define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ 36*4882a593Smuzhiyun #define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ 37*4882a593Smuzhiyun #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ 38*4882a593Smuzhiyun #define AT91_PMC_GCKRDY 24 /* Generated Clocks */ 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif 42