1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_AST2600_CLOCK_H 3*4882a593Smuzhiyun #define DT_BINDINGS_AST2600_CLOCK_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define ASPEED_CLK_GATE_ECLK 0 6*4882a593Smuzhiyun #define ASPEED_CLK_GATE_GCLK 1 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MCLK 2 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define ASPEED_CLK_GATE_VCLK 3 11*4882a593Smuzhiyun #define ASPEED_CLK_GATE_BCLK 4 12*4882a593Smuzhiyun #define ASPEED_CLK_GATE_DCLK 5 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define ASPEED_CLK_GATE_LCLK 6 15*4882a593Smuzhiyun #define ASPEED_CLK_GATE_LHCCLK 7 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ASPEED_CLK_GATE_D1CLK 8 18*4882a593Smuzhiyun #define ASPEED_CLK_GATE_YCLK 9 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ASPEED_CLK_GATE_REF0CLK 10 21*4882a593Smuzhiyun #define ASPEED_CLK_GATE_REF1CLK 11 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define ASPEED_CLK_GATE_ESPICLK 12 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBUHCICLK 13 26*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBPORT1CLK 14 27*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBPORT2CLK 15 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define ASPEED_CLK_GATE_RSACLK 16 30*4882a593Smuzhiyun #define ASPEED_CLK_GATE_RVASCLK 17 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC1CLK 18 33*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC2CLK 19 34*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC3CLK 20 35*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC4CLK 21 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART1CLK 22 38*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART2CLK 23 39*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART3CLK 24 40*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART4CLK 25 41*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART5CLK 26 42*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART6CLK 27 43*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART7CLK 28 44*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART8CLK 29 45*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART9CLK 30 46*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART10CLK 31 47*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART11CLK 32 48*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART12CLK 33 49*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART13CLK 34 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define ASPEED_CLK_GATE_SDCLK 35 52*4882a593Smuzhiyun #define ASPEED_CLK_GATE_EMMCCLK 36 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C0CLK 37 55*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C1CLK 38 56*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C2CLK 39 57*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C3CLK 40 58*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C4CLK 41 59*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C5CLK 42 60*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C6CLK 43 61*4882a593Smuzhiyun #define ASPEED_CLK_GATE_I3C7CLK 44 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define ASPEED_CLK_GATE_FSICLK 45 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define ASPEED_CLK_HPLL 46 66*4882a593Smuzhiyun #define ASPEED_CLK_MPLL 47 67*4882a593Smuzhiyun #define ASPEED_CLK_DPLL 48 68*4882a593Smuzhiyun #define ASPEED_CLK_EPLL 49 69*4882a593Smuzhiyun #define ASPEED_CLK_APLL 50 70*4882a593Smuzhiyun #define ASPEED_CLK_AHB 51 71*4882a593Smuzhiyun #define ASPEED_CLK_APB1 52 72*4882a593Smuzhiyun #define ASPEED_CLK_APB2 53 73*4882a593Smuzhiyun #define ASPEED_CLK_BCLK 54 74*4882a593Smuzhiyun #define ASPEED_CLK_D1CLK 55 75*4882a593Smuzhiyun #define ASPEED_CLK_VCLK 56 76*4882a593Smuzhiyun #define ASPEED_CLK_LHCLK 57 77*4882a593Smuzhiyun #define ASPEED_CLK_UART 58 78*4882a593Smuzhiyun #define ASPEED_CLK_UARTX 59 79*4882a593Smuzhiyun #define ASPEED_CLK_SDIO 60 80*4882a593Smuzhiyun #define ASPEED_CLK_EMMC 61 81*4882a593Smuzhiyun #define ASPEED_CLK_ECLK 62 82*4882a593Smuzhiyun #define ASPEED_CLK_ECLK_MUX 63 83*4882a593Smuzhiyun #define ASPEED_CLK_MAC12 64 84*4882a593Smuzhiyun #define ASPEED_CLK_MAC34 65 85*4882a593Smuzhiyun #define ASPEED_CLK_USBPHY_40M 66 86*4882a593Smuzhiyun #define ASPEED_CLK_MAC1RCLK 67 87*4882a593Smuzhiyun #define ASPEED_CLK_MAC2RCLK 68 88*4882a593Smuzhiyun #define ASPEED_CLK_MAC3RCLK 69 89*4882a593Smuzhiyun #define ASPEED_CLK_MAC4RCLK 70 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Only list resets here that are not part of a gate */ 92*4882a593Smuzhiyun #define ASPEED_RESET_ADC 55 93*4882a593Smuzhiyun #define ASPEED_RESET_JTAG_MASTER2 54 94*4882a593Smuzhiyun #define ASPEED_RESET_I3C_DMA 39 95*4882a593Smuzhiyun #define ASPEED_RESET_PWM 37 96*4882a593Smuzhiyun #define ASPEED_RESET_PECI 36 97*4882a593Smuzhiyun #define ASPEED_RESET_MII 35 98*4882a593Smuzhiyun #define ASPEED_RESET_I2C 34 99*4882a593Smuzhiyun #define ASPEED_RESET_H2X 31 100*4882a593Smuzhiyun #define ASPEED_RESET_GP_MCU 30 101*4882a593Smuzhiyun #define ASPEED_RESET_DP_MCU 29 102*4882a593Smuzhiyun #define ASPEED_RESET_DP 28 103*4882a593Smuzhiyun #define ASPEED_RESET_RC_XDMA 27 104*4882a593Smuzhiyun #define ASPEED_RESET_GRAPHICS 26 105*4882a593Smuzhiyun #define ASPEED_RESET_DEV_XDMA 25 106*4882a593Smuzhiyun #define ASPEED_RESET_DEV_MCTP 24 107*4882a593Smuzhiyun #define ASPEED_RESET_RC_MCTP 23 108*4882a593Smuzhiyun #define ASPEED_RESET_JTAG_MASTER 22 109*4882a593Smuzhiyun #define ASPEED_RESET_PCIE_DEV_O 21 110*4882a593Smuzhiyun #define ASPEED_RESET_PCIE_DEV_OEN 20 111*4882a593Smuzhiyun #define ASPEED_RESET_PCIE_RC_O 19 112*4882a593Smuzhiyun #define ASPEED_RESET_PCIE_RC_OEN 18 113*4882a593Smuzhiyun #define ASPEED_RESET_PCI_DP 5 114*4882a593Smuzhiyun #define ASPEED_RESET_AHB 1 115*4882a593Smuzhiyun #define ASPEED_RESET_SDRAM 0 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118