1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef DT_BINDINGS_ASPEED_CLOCK_H 4*4882a593Smuzhiyun #define DT_BINDINGS_ASPEED_CLOCK_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define ASPEED_CLK_GATE_ECLK 0 7*4882a593Smuzhiyun #define ASPEED_CLK_GATE_GCLK 1 8*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MCLK 2 9*4882a593Smuzhiyun #define ASPEED_CLK_GATE_VCLK 3 10*4882a593Smuzhiyun #define ASPEED_CLK_GATE_BCLK 4 11*4882a593Smuzhiyun #define ASPEED_CLK_GATE_DCLK 5 12*4882a593Smuzhiyun #define ASPEED_CLK_GATE_REFCLK 6 13*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBPORT2CLK 7 14*4882a593Smuzhiyun #define ASPEED_CLK_GATE_LCLK 8 15*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBUHCICLK 9 16*4882a593Smuzhiyun #define ASPEED_CLK_GATE_D1CLK 10 17*4882a593Smuzhiyun #define ASPEED_CLK_GATE_YCLK 11 18*4882a593Smuzhiyun #define ASPEED_CLK_GATE_USBPORT1CLK 12 19*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART1CLK 13 20*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART2CLK 14 21*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART5CLK 15 22*4882a593Smuzhiyun #define ASPEED_CLK_GATE_ESPICLK 16 23*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC1CLK 17 24*4882a593Smuzhiyun #define ASPEED_CLK_GATE_MAC2CLK 18 25*4882a593Smuzhiyun #define ASPEED_CLK_GATE_RSACLK 19 26*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART3CLK 20 27*4882a593Smuzhiyun #define ASPEED_CLK_GATE_UART4CLK 21 28*4882a593Smuzhiyun #define ASPEED_CLK_GATE_SDCLK 22 29*4882a593Smuzhiyun #define ASPEED_CLK_GATE_LHCCLK 23 30*4882a593Smuzhiyun #define ASPEED_CLK_HPLL 24 31*4882a593Smuzhiyun #define ASPEED_CLK_AHB 25 32*4882a593Smuzhiyun #define ASPEED_CLK_APB 26 33*4882a593Smuzhiyun #define ASPEED_CLK_UART 27 34*4882a593Smuzhiyun #define ASPEED_CLK_SDIO 28 35*4882a593Smuzhiyun #define ASPEED_CLK_ECLK 29 36*4882a593Smuzhiyun #define ASPEED_CLK_ECLK_MUX 30 37*4882a593Smuzhiyun #define ASPEED_CLK_LHCLK 31 38*4882a593Smuzhiyun #define ASPEED_CLK_MAC 32 39*4882a593Smuzhiyun #define ASPEED_CLK_BCLK 33 40*4882a593Smuzhiyun #define ASPEED_CLK_MPLL 34 41*4882a593Smuzhiyun #define ASPEED_CLK_24M 35 42*4882a593Smuzhiyun #define ASPEED_CLK_MAC1RCLK 36 43*4882a593Smuzhiyun #define ASPEED_CLK_MAC2RCLK 37 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ASPEED_RESET_XDMA 0 46*4882a593Smuzhiyun #define ASPEED_RESET_MCTP 1 47*4882a593Smuzhiyun #define ASPEED_RESET_ADC 2 48*4882a593Smuzhiyun #define ASPEED_RESET_JTAG_MASTER 3 49*4882a593Smuzhiyun #define ASPEED_RESET_MIC 4 50*4882a593Smuzhiyun #define ASPEED_RESET_PWM 5 51*4882a593Smuzhiyun #define ASPEED_RESET_PECI 6 52*4882a593Smuzhiyun #define ASPEED_RESET_I2C 7 53*4882a593Smuzhiyun #define ASPEED_RESET_AHB 8 54*4882a593Smuzhiyun #define ASPEED_RESET_CRT1 9 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57