1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_AM3_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_AM3_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define AM3_CLKCTRL_OFFSET 0x0 9*4882a593Smuzhiyun #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* l4_per clocks */ 14*4882a593Smuzhiyun #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 15*4882a593Smuzhiyun #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) 16*4882a593Smuzhiyun #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) 17*4882a593Smuzhiyun #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) 18*4882a593Smuzhiyun #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) 19*4882a593Smuzhiyun #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) 20*4882a593Smuzhiyun #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) 21*4882a593Smuzhiyun #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) 22*4882a593Smuzhiyun #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) 23*4882a593Smuzhiyun #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) 24*4882a593Smuzhiyun #define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) 25*4882a593Smuzhiyun #define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) 26*4882a593Smuzhiyun #define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) 27*4882a593Smuzhiyun #define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) 28*4882a593Smuzhiyun #define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) 29*4882a593Smuzhiyun #define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) 30*4882a593Smuzhiyun #define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) 31*4882a593Smuzhiyun #define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) 32*4882a593Smuzhiyun #define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) 33*4882a593Smuzhiyun #define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) 34*4882a593Smuzhiyun #define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) 35*4882a593Smuzhiyun #define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) 36*4882a593Smuzhiyun #define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) 37*4882a593Smuzhiyun #define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) 38*4882a593Smuzhiyun #define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) 39*4882a593Smuzhiyun #define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) 40*4882a593Smuzhiyun #define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) 41*4882a593Smuzhiyun #define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) 42*4882a593Smuzhiyun #define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) 43*4882a593Smuzhiyun #define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) 44*4882a593Smuzhiyun #define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) 45*4882a593Smuzhiyun #define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) 46*4882a593Smuzhiyun #define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) 47*4882a593Smuzhiyun #define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) 48*4882a593Smuzhiyun #define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) 49*4882a593Smuzhiyun #define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) 50*4882a593Smuzhiyun #define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) 51*4882a593Smuzhiyun #define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) 52*4882a593Smuzhiyun #define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) 53*4882a593Smuzhiyun #define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) 54*4882a593Smuzhiyun #define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) 55*4882a593Smuzhiyun #define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) 56*4882a593Smuzhiyun #define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) 57*4882a593Smuzhiyun #define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) 58*4882a593Smuzhiyun #define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) 59*4882a593Smuzhiyun #define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) 60*4882a593Smuzhiyun #define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) 61*4882a593Smuzhiyun #define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) 62*4882a593Smuzhiyun #define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) 63*4882a593Smuzhiyun #define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) 64*4882a593Smuzhiyun #define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) 65*4882a593Smuzhiyun #define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) 66*4882a593Smuzhiyun #define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* l4_wkup clocks */ 69*4882a593Smuzhiyun #define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 70*4882a593Smuzhiyun #define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) 71*4882a593Smuzhiyun #define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) 72*4882a593Smuzhiyun #define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) 73*4882a593Smuzhiyun #define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) 74*4882a593Smuzhiyun #define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) 75*4882a593Smuzhiyun #define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) 76*4882a593Smuzhiyun #define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) 77*4882a593Smuzhiyun #define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) 78*4882a593Smuzhiyun #define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) 79*4882a593Smuzhiyun #define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) 80*4882a593Smuzhiyun #define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) 81*4882a593Smuzhiyun #define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) 82*4882a593Smuzhiyun #define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* mpu clocks */ 85*4882a593Smuzhiyun #define AM3_MPU_CLKCTRL_OFFSET 0x4 86*4882a593Smuzhiyun #define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) 87*4882a593Smuzhiyun #define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* l4_rtc clocks */ 90*4882a593Smuzhiyun #define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* gfx_l3 clocks */ 93*4882a593Smuzhiyun #define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 94*4882a593Smuzhiyun #define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) 95*4882a593Smuzhiyun #define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* l4_cefuse clocks */ 98*4882a593Smuzhiyun #define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 99*4882a593Smuzhiyun #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) 100*4882a593Smuzhiyun #define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* XXX: Compatibility part end */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* l4ls clocks */ 105*4882a593Smuzhiyun #define AM3_L4LS_CLKCTRL_OFFSET 0x38 106*4882a593Smuzhiyun #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) 107*4882a593Smuzhiyun #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) 108*4882a593Smuzhiyun #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) 109*4882a593Smuzhiyun #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) 110*4882a593Smuzhiyun #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) 111*4882a593Smuzhiyun #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) 112*4882a593Smuzhiyun #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) 113*4882a593Smuzhiyun #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) 114*4882a593Smuzhiyun #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) 115*4882a593Smuzhiyun #define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) 116*4882a593Smuzhiyun #define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) 117*4882a593Smuzhiyun #define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) 118*4882a593Smuzhiyun #define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) 119*4882a593Smuzhiyun #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) 120*4882a593Smuzhiyun #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) 121*4882a593Smuzhiyun #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) 122*4882a593Smuzhiyun #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) 123*4882a593Smuzhiyun #define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) 124*4882a593Smuzhiyun #define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) 125*4882a593Smuzhiyun #define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) 126*4882a593Smuzhiyun #define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) 127*4882a593Smuzhiyun #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) 128*4882a593Smuzhiyun #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) 129*4882a593Smuzhiyun #define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) 130*4882a593Smuzhiyun #define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) 131*4882a593Smuzhiyun #define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) 132*4882a593Smuzhiyun #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) 133*4882a593Smuzhiyun #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) 134*4882a593Smuzhiyun #define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) 135*4882a593Smuzhiyun #define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) 136*4882a593Smuzhiyun #define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) 137*4882a593Smuzhiyun #define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* l3s clocks */ 140*4882a593Smuzhiyun #define AM3_L3S_CLKCTRL_OFFSET 0x1c 141*4882a593Smuzhiyun #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) 142*4882a593Smuzhiyun #define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) 143*4882a593Smuzhiyun #define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) 144*4882a593Smuzhiyun #define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) 145*4882a593Smuzhiyun #define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) 146*4882a593Smuzhiyun #define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* l3 clocks */ 149*4882a593Smuzhiyun #define AM3_L3_CLKCTRL_OFFSET 0x24 150*4882a593Smuzhiyun #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) 151*4882a593Smuzhiyun #define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) 152*4882a593Smuzhiyun #define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) 153*4882a593Smuzhiyun #define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) 154*4882a593Smuzhiyun #define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) 155*4882a593Smuzhiyun #define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) 156*4882a593Smuzhiyun #define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) 157*4882a593Smuzhiyun #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) 158*4882a593Smuzhiyun #define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) 159*4882a593Smuzhiyun #define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) 160*4882a593Smuzhiyun #define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* l4hs clocks */ 163*4882a593Smuzhiyun #define AM3_L4HS_CLKCTRL_OFFSET 0x120 164*4882a593Smuzhiyun #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) 165*4882a593Smuzhiyun #define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* pruss_ocp clocks */ 168*4882a593Smuzhiyun #define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 169*4882a593Smuzhiyun #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) 170*4882a593Smuzhiyun #define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* cpsw_125mhz clocks */ 173*4882a593Smuzhiyun #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* lcdc clocks */ 176*4882a593Smuzhiyun #define AM3_LCDC_CLKCTRL_OFFSET 0x18 177*4882a593Smuzhiyun #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) 178*4882a593Smuzhiyun #define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* clk_24mhz clocks */ 181*4882a593Smuzhiyun #define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c 182*4882a593Smuzhiyun #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) 183*4882a593Smuzhiyun #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* l4_wkup clocks */ 186*4882a593Smuzhiyun #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 187*4882a593Smuzhiyun #define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) 188*4882a593Smuzhiyun #define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) 189*4882a593Smuzhiyun #define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) 190*4882a593Smuzhiyun #define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) 191*4882a593Smuzhiyun #define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) 192*4882a593Smuzhiyun #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) 193*4882a593Smuzhiyun #define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) 194*4882a593Smuzhiyun #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) 195*4882a593Smuzhiyun #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* l3_aon clocks */ 198*4882a593Smuzhiyun #define AM3_L3_AON_CLKCTRL_OFFSET 0x14 199*4882a593Smuzhiyun #define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) 200*4882a593Smuzhiyun #define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* l4_wkup_aon clocks */ 203*4882a593Smuzhiyun #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 204*4882a593Smuzhiyun #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) 205*4882a593Smuzhiyun #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* mpu clocks */ 208*4882a593Smuzhiyun #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* l4_rtc clocks */ 211*4882a593Smuzhiyun #define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* gfx_l3 clocks */ 214*4882a593Smuzhiyun #define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun /* l4_cefuse clocks */ 217*4882a593Smuzhiyun #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #endif 220