1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ASM9260_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ASM9260_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* ahb gate */ 10*4882a593Smuzhiyun #define CLKID_AHB_ROM 0 11*4882a593Smuzhiyun #define CLKID_AHB_RAM 1 12*4882a593Smuzhiyun #define CLKID_AHB_GPIO 2 13*4882a593Smuzhiyun #define CLKID_AHB_MAC 3 14*4882a593Smuzhiyun #define CLKID_AHB_EMI 4 15*4882a593Smuzhiyun #define CLKID_AHB_USB0 5 16*4882a593Smuzhiyun #define CLKID_AHB_USB1 6 17*4882a593Smuzhiyun #define CLKID_AHB_DMA0 7 18*4882a593Smuzhiyun #define CLKID_AHB_DMA1 8 19*4882a593Smuzhiyun #define CLKID_AHB_UART0 9 20*4882a593Smuzhiyun #define CLKID_AHB_UART1 10 21*4882a593Smuzhiyun #define CLKID_AHB_UART2 11 22*4882a593Smuzhiyun #define CLKID_AHB_UART3 12 23*4882a593Smuzhiyun #define CLKID_AHB_UART4 13 24*4882a593Smuzhiyun #define CLKID_AHB_UART5 14 25*4882a593Smuzhiyun #define CLKID_AHB_UART6 15 26*4882a593Smuzhiyun #define CLKID_AHB_UART7 16 27*4882a593Smuzhiyun #define CLKID_AHB_UART8 17 28*4882a593Smuzhiyun #define CLKID_AHB_UART9 18 29*4882a593Smuzhiyun #define CLKID_AHB_I2S0 19 30*4882a593Smuzhiyun #define CLKID_AHB_I2C0 20 31*4882a593Smuzhiyun #define CLKID_AHB_I2C1 21 32*4882a593Smuzhiyun #define CLKID_AHB_SSP0 22 33*4882a593Smuzhiyun #define CLKID_AHB_IOCONFIG 23 34*4882a593Smuzhiyun #define CLKID_AHB_WDT 24 35*4882a593Smuzhiyun #define CLKID_AHB_CAN0 25 36*4882a593Smuzhiyun #define CLKID_AHB_CAN1 26 37*4882a593Smuzhiyun #define CLKID_AHB_MPWM 27 38*4882a593Smuzhiyun #define CLKID_AHB_SPI0 28 39*4882a593Smuzhiyun #define CLKID_AHB_SPI1 29 40*4882a593Smuzhiyun #define CLKID_AHB_QEI 30 41*4882a593Smuzhiyun #define CLKID_AHB_QUADSPI0 31 42*4882a593Smuzhiyun #define CLKID_AHB_CAMIF 32 43*4882a593Smuzhiyun #define CLKID_AHB_LCDIF 33 44*4882a593Smuzhiyun #define CLKID_AHB_TIMER0 34 45*4882a593Smuzhiyun #define CLKID_AHB_TIMER1 35 46*4882a593Smuzhiyun #define CLKID_AHB_TIMER2 36 47*4882a593Smuzhiyun #define CLKID_AHB_TIMER3 37 48*4882a593Smuzhiyun #define CLKID_AHB_IRQ 38 49*4882a593Smuzhiyun #define CLKID_AHB_RTC 39 50*4882a593Smuzhiyun #define CLKID_AHB_NAND 40 51*4882a593Smuzhiyun #define CLKID_AHB_ADC0 41 52*4882a593Smuzhiyun #define CLKID_AHB_LED 42 53*4882a593Smuzhiyun #define CLKID_AHB_DAC0 43 54*4882a593Smuzhiyun #define CLKID_AHB_LCD 44 55*4882a593Smuzhiyun #define CLKID_AHB_I2S1 45 56*4882a593Smuzhiyun #define CLKID_AHB_MAC1 46 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* devider */ 59*4882a593Smuzhiyun #define CLKID_SYS_CPU 47 60*4882a593Smuzhiyun #define CLKID_SYS_AHB 48 61*4882a593Smuzhiyun #define CLKID_SYS_I2S0M 49 62*4882a593Smuzhiyun #define CLKID_SYS_I2S0S 50 63*4882a593Smuzhiyun #define CLKID_SYS_I2S1M 51 64*4882a593Smuzhiyun #define CLKID_SYS_I2S1S 52 65*4882a593Smuzhiyun #define CLKID_SYS_UART0 53 66*4882a593Smuzhiyun #define CLKID_SYS_UART1 54 67*4882a593Smuzhiyun #define CLKID_SYS_UART2 55 68*4882a593Smuzhiyun #define CLKID_SYS_UART3 56 69*4882a593Smuzhiyun #define CLKID_SYS_UART4 56 70*4882a593Smuzhiyun #define CLKID_SYS_UART5 57 71*4882a593Smuzhiyun #define CLKID_SYS_UART6 58 72*4882a593Smuzhiyun #define CLKID_SYS_UART7 59 73*4882a593Smuzhiyun #define CLKID_SYS_UART8 60 74*4882a593Smuzhiyun #define CLKID_SYS_UART9 61 75*4882a593Smuzhiyun #define CLKID_SYS_SPI0 62 76*4882a593Smuzhiyun #define CLKID_SYS_SPI1 63 77*4882a593Smuzhiyun #define CLKID_SYS_QUADSPI 64 78*4882a593Smuzhiyun #define CLKID_SYS_SSP0 65 79*4882a593Smuzhiyun #define CLKID_SYS_NAND 66 80*4882a593Smuzhiyun #define CLKID_SYS_TRACE 67 81*4882a593Smuzhiyun #define CLKID_SYS_CAMM 68 82*4882a593Smuzhiyun #define CLKID_SYS_WDT 69 83*4882a593Smuzhiyun #define CLKID_SYS_CLKOUT 70 84*4882a593Smuzhiyun #define CLKID_SYS_MAC 71 85*4882a593Smuzhiyun #define CLKID_SYS_LCD 72 86*4882a593Smuzhiyun #define CLKID_SYS_ADCANA 73 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define MAX_CLKS 74 89*4882a593Smuzhiyun #endif 90