1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019, Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __AGILEX_CLOCK_H 7*4882a593Smuzhiyun #define __AGILEX_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* fixed rate clocks */ 10*4882a593Smuzhiyun #define AGILEX_OSC1 0 11*4882a593Smuzhiyun #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 12*4882a593Smuzhiyun #define AGILEX_CB_INTOSC_LS_CLK 2 13*4882a593Smuzhiyun #define AGILEX_L4_SYS_FREE_CLK 3 14*4882a593Smuzhiyun #define AGILEX_F2S_FREE_CLK 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* PLL clocks */ 17*4882a593Smuzhiyun #define AGILEX_MAIN_PLL_CLK 5 18*4882a593Smuzhiyun #define AGILEX_MAIN_PLL_C0_CLK 6 19*4882a593Smuzhiyun #define AGILEX_MAIN_PLL_C1_CLK 7 20*4882a593Smuzhiyun #define AGILEX_MAIN_PLL_C2_CLK 8 21*4882a593Smuzhiyun #define AGILEX_MAIN_PLL_C3_CLK 9 22*4882a593Smuzhiyun #define AGILEX_PERIPH_PLL_CLK 10 23*4882a593Smuzhiyun #define AGILEX_PERIPH_PLL_C0_CLK 11 24*4882a593Smuzhiyun #define AGILEX_PERIPH_PLL_C1_CLK 12 25*4882a593Smuzhiyun #define AGILEX_PERIPH_PLL_C2_CLK 13 26*4882a593Smuzhiyun #define AGILEX_PERIPH_PLL_C3_CLK 14 27*4882a593Smuzhiyun #define AGILEX_MPU_FREE_CLK 15 28*4882a593Smuzhiyun #define AGILEX_MPU_CCU_CLK 16 29*4882a593Smuzhiyun #define AGILEX_BOOT_CLK 17 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* fixed factor clocks */ 32*4882a593Smuzhiyun #define AGILEX_L3_MAIN_FREE_CLK 18 33*4882a593Smuzhiyun #define AGILEX_NOC_FREE_CLK 19 34*4882a593Smuzhiyun #define AGILEX_S2F_USR0_CLK 20 35*4882a593Smuzhiyun #define AGILEX_NOC_CLK 21 36*4882a593Smuzhiyun #define AGILEX_EMAC_A_FREE_CLK 22 37*4882a593Smuzhiyun #define AGILEX_EMAC_B_FREE_CLK 23 38*4882a593Smuzhiyun #define AGILEX_EMAC_PTP_FREE_CLK 24 39*4882a593Smuzhiyun #define AGILEX_GPIO_DB_FREE_CLK 25 40*4882a593Smuzhiyun #define AGILEX_SDMMC_FREE_CLK 26 41*4882a593Smuzhiyun #define AGILEX_S2F_USER0_FREE_CLK 27 42*4882a593Smuzhiyun #define AGILEX_S2F_USER1_FREE_CLK 28 43*4882a593Smuzhiyun #define AGILEX_PSI_REF_FREE_CLK 29 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Gate clocks */ 46*4882a593Smuzhiyun #define AGILEX_MPU_CLK 30 47*4882a593Smuzhiyun #define AGILEX_MPU_L2RAM_CLK 31 48*4882a593Smuzhiyun #define AGILEX_MPU_PERIPH_CLK 32 49*4882a593Smuzhiyun #define AGILEX_L4_MAIN_CLK 33 50*4882a593Smuzhiyun #define AGILEX_L4_MP_CLK 34 51*4882a593Smuzhiyun #define AGILEX_L4_SP_CLK 35 52*4882a593Smuzhiyun #define AGILEX_CS_AT_CLK 36 53*4882a593Smuzhiyun #define AGILEX_CS_TRACE_CLK 37 54*4882a593Smuzhiyun #define AGILEX_CS_PDBG_CLK 38 55*4882a593Smuzhiyun #define AGILEX_CS_TIMER_CLK 39 56*4882a593Smuzhiyun #define AGILEX_S2F_USER0_CLK 40 57*4882a593Smuzhiyun #define AGILEX_EMAC0_CLK 41 58*4882a593Smuzhiyun #define AGILEX_EMAC1_CLK 43 59*4882a593Smuzhiyun #define AGILEX_EMAC2_CLK 44 60*4882a593Smuzhiyun #define AGILEX_EMAC_PTP_CLK 45 61*4882a593Smuzhiyun #define AGILEX_GPIO_DB_CLK 46 62*4882a593Smuzhiyun #define AGILEX_NAND_CLK 47 63*4882a593Smuzhiyun #define AGILEX_PSI_REF_CLK 48 64*4882a593Smuzhiyun #define AGILEX_S2F_USER1_CLK 49 65*4882a593Smuzhiyun #define AGILEX_SDMMC_CLK 50 66*4882a593Smuzhiyun #define AGILEX_SPI_M_CLK 51 67*4882a593Smuzhiyun #define AGILEX_USB_CLK 52 68*4882a593Smuzhiyun #define AGILEX_NAND_X_CLK 53 69*4882a593Smuzhiyun #define AGILEX_NAND_ECC_CLK 54 70*4882a593Smuzhiyun #define AGILEX_NUM_CLKS 55 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __AGILEX_CLOCK_H */ 73