1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun // 3*4882a593Smuzhiyun // Device Tree binding constants for Actions Semi S900 Clock Management Unit 4*4882a593Smuzhiyun // 5*4882a593Smuzhiyun // Copyright (c) 2014 Actions Semi Inc. 6*4882a593Smuzhiyun // Copyright (c) 2018 Linaro Ltd. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_S900_CMU_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_S900_CMU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_NONE 0 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* fixed rate clocks */ 14*4882a593Smuzhiyun #define CLK_LOSC 1 15*4882a593Smuzhiyun #define CLK_HOSC 2 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* pll clocks */ 18*4882a593Smuzhiyun #define CLK_CORE_PLL 3 19*4882a593Smuzhiyun #define CLK_DEV_PLL 4 20*4882a593Smuzhiyun #define CLK_DDR_PLL 5 21*4882a593Smuzhiyun #define CLK_NAND_PLL 6 22*4882a593Smuzhiyun #define CLK_DISPLAY_PLL 7 23*4882a593Smuzhiyun #define CLK_DSI_PLL 8 24*4882a593Smuzhiyun #define CLK_ASSIST_PLL 9 25*4882a593Smuzhiyun #define CLK_AUDIO_PLL 10 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* system clock */ 28*4882a593Smuzhiyun #define CLK_CPU 15 29*4882a593Smuzhiyun #define CLK_DEV 16 30*4882a593Smuzhiyun #define CLK_NOC 17 31*4882a593Smuzhiyun #define CLK_NOC_MUX 18 32*4882a593Smuzhiyun #define CLK_NOC_DIV 19 33*4882a593Smuzhiyun #define CLK_AHB 20 34*4882a593Smuzhiyun #define CLK_APB 21 35*4882a593Smuzhiyun #define CLK_DMAC 22 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* peripheral device clock */ 38*4882a593Smuzhiyun #define CLK_GPIO 23 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CLK_BISP 24 41*4882a593Smuzhiyun #define CLK_CSI0 25 42*4882a593Smuzhiyun #define CLK_CSI1 26 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CLK_DE0 27 45*4882a593Smuzhiyun #define CLK_DE1 28 46*4882a593Smuzhiyun #define CLK_DE2 29 47*4882a593Smuzhiyun #define CLK_DE3 30 48*4882a593Smuzhiyun #define CLK_DSI 32 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CLK_GPU 33 51*4882a593Smuzhiyun #define CLK_GPU_CORE 34 52*4882a593Smuzhiyun #define CLK_GPU_MEM 35 53*4882a593Smuzhiyun #define CLK_GPU_SYS 36 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CLK_HDE 37 56*4882a593Smuzhiyun #define CLK_I2C0 38 57*4882a593Smuzhiyun #define CLK_I2C1 39 58*4882a593Smuzhiyun #define CLK_I2C2 40 59*4882a593Smuzhiyun #define CLK_I2C3 41 60*4882a593Smuzhiyun #define CLK_I2C4 42 61*4882a593Smuzhiyun #define CLK_I2C5 43 62*4882a593Smuzhiyun #define CLK_I2SRX 44 63*4882a593Smuzhiyun #define CLK_I2STX 45 64*4882a593Smuzhiyun #define CLK_IMX 46 65*4882a593Smuzhiyun #define CLK_LCD 47 66*4882a593Smuzhiyun #define CLK_NAND0 48 67*4882a593Smuzhiyun #define CLK_NAND1 49 68*4882a593Smuzhiyun #define CLK_PWM0 50 69*4882a593Smuzhiyun #define CLK_PWM1 51 70*4882a593Smuzhiyun #define CLK_PWM2 52 71*4882a593Smuzhiyun #define CLK_PWM3 53 72*4882a593Smuzhiyun #define CLK_PWM4 54 73*4882a593Smuzhiyun #define CLK_PWM5 55 74*4882a593Smuzhiyun #define CLK_SD0 56 75*4882a593Smuzhiyun #define CLK_SD1 57 76*4882a593Smuzhiyun #define CLK_SD2 58 77*4882a593Smuzhiyun #define CLK_SD3 59 78*4882a593Smuzhiyun #define CLK_SENSOR 60 79*4882a593Smuzhiyun #define CLK_SPEED_SENSOR 61 80*4882a593Smuzhiyun #define CLK_SPI0 62 81*4882a593Smuzhiyun #define CLK_SPI1 63 82*4882a593Smuzhiyun #define CLK_SPI2 64 83*4882a593Smuzhiyun #define CLK_SPI3 65 84*4882a593Smuzhiyun #define CLK_THERMAL_SENSOR 66 85*4882a593Smuzhiyun #define CLK_UART0 67 86*4882a593Smuzhiyun #define CLK_UART1 68 87*4882a593Smuzhiyun #define CLK_UART2 69 88*4882a593Smuzhiyun #define CLK_UART3 70 89*4882a593Smuzhiyun #define CLK_UART4 71 90*4882a593Smuzhiyun #define CLK_UART5 72 91*4882a593Smuzhiyun #define CLK_UART6 73 92*4882a593Smuzhiyun #define CLK_VCE 74 93*4882a593Smuzhiyun #define CLK_VDE 75 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CLK_USB3_480MPLL0 76 96*4882a593Smuzhiyun #define CLK_USB3_480MPHY0 77 97*4882a593Smuzhiyun #define CLK_USB3_5GPHY 78 98*4882a593Smuzhiyun #define CLK_USB3_CCE 79 99*4882a593Smuzhiyun #define CLK_USB3_MAC 80 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define CLK_TIMER 83 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CLK_HDMI_AUDIO 84 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define CLK_24M 85 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define CLK_EDP 86 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CLK_24M_EDP 87 110*4882a593Smuzhiyun #define CLK_EDP_PLL 88 111*4882a593Smuzhiyun #define CLK_EDP_LINK 89 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define CLK_USB2H0_PLLEN 90 114*4882a593Smuzhiyun #define CLK_USB2H0_PHY 91 115*4882a593Smuzhiyun #define CLK_USB2H0_CCE 92 116*4882a593Smuzhiyun #define CLK_USB2H1_PLLEN 93 117*4882a593Smuzhiyun #define CLK_USB2H1_PHY 94 118*4882a593Smuzhiyun #define CLK_USB2H1_CCE 95 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define CLK_DDR0 96 121*4882a593Smuzhiyun #define CLK_DDR1 97 122*4882a593Smuzhiyun #define CLK_DMM 98 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define CLK_ETH_MAC 99 125*4882a593Smuzhiyun #define CLK_RMII_REF 100 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define CLK_NR_CLKS (CLK_RMII_REF + 1) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ 130