1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Device Tree binding constants for Actions Semi S700 Clock Management Unit 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Actions Semi Inc. 6*4882a593Smuzhiyun * Author: David Liu <liuwei@actions-semi.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Pathiban Nallathambi <pn@denx.de> 9*4882a593Smuzhiyun * Author: Saravanan Sekar <sravanhome@gmail.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_S700_H 13*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_S700_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_NONE 0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* pll clocks */ 18*4882a593Smuzhiyun #define CLK_CORE_PLL 1 19*4882a593Smuzhiyun #define CLK_DEV_PLL 2 20*4882a593Smuzhiyun #define CLK_DDR_PLL 3 21*4882a593Smuzhiyun #define CLK_NAND_PLL 4 22*4882a593Smuzhiyun #define CLK_DISPLAY_PLL 5 23*4882a593Smuzhiyun #define CLK_TVOUT_PLL 6 24*4882a593Smuzhiyun #define CLK_CVBS_PLL 7 25*4882a593Smuzhiyun #define CLK_AUDIO_PLL 8 26*4882a593Smuzhiyun #define CLK_ETHERNET_PLL 9 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* system clock */ 29*4882a593Smuzhiyun #define CLK_CPU 10 30*4882a593Smuzhiyun #define CLK_DEV 11 31*4882a593Smuzhiyun #define CLK_AHB 12 32*4882a593Smuzhiyun #define CLK_APB 13 33*4882a593Smuzhiyun #define CLK_DMAC 14 34*4882a593Smuzhiyun #define CLK_NOC0_CLK_MUX 15 35*4882a593Smuzhiyun #define CLK_NOC1_CLK_MUX 16 36*4882a593Smuzhiyun #define CLK_HP_CLK_MUX 17 37*4882a593Smuzhiyun #define CLK_HP_CLK_DIV 18 38*4882a593Smuzhiyun #define CLK_NOC1_CLK_DIV 19 39*4882a593Smuzhiyun #define CLK_NOC0 20 40*4882a593Smuzhiyun #define CLK_NOC1 21 41*4882a593Smuzhiyun #define CLK_SENOR_SRC 22 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* peripheral device clock */ 44*4882a593Smuzhiyun #define CLK_GPIO 23 45*4882a593Smuzhiyun #define CLK_TIMER 24 46*4882a593Smuzhiyun #define CLK_DSI 25 47*4882a593Smuzhiyun #define CLK_CSI 26 48*4882a593Smuzhiyun #define CLK_SI 27 49*4882a593Smuzhiyun #define CLK_DE 28 50*4882a593Smuzhiyun #define CLK_HDE 29 51*4882a593Smuzhiyun #define CLK_VDE 30 52*4882a593Smuzhiyun #define CLK_VCE 31 53*4882a593Smuzhiyun #define CLK_NAND 32 54*4882a593Smuzhiyun #define CLK_SD0 33 55*4882a593Smuzhiyun #define CLK_SD1 34 56*4882a593Smuzhiyun #define CLK_SD2 35 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CLK_UART0 36 59*4882a593Smuzhiyun #define CLK_UART1 37 60*4882a593Smuzhiyun #define CLK_UART2 38 61*4882a593Smuzhiyun #define CLK_UART3 39 62*4882a593Smuzhiyun #define CLK_UART4 40 63*4882a593Smuzhiyun #define CLK_UART5 41 64*4882a593Smuzhiyun #define CLK_UART6 42 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CLK_PWM0 43 67*4882a593Smuzhiyun #define CLK_PWM1 44 68*4882a593Smuzhiyun #define CLK_PWM2 45 69*4882a593Smuzhiyun #define CLK_PWM3 46 70*4882a593Smuzhiyun #define CLK_PWM4 47 71*4882a593Smuzhiyun #define CLK_PWM5 48 72*4882a593Smuzhiyun #define CLK_GPU3D 49 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define CLK_I2C0 50 75*4882a593Smuzhiyun #define CLK_I2C1 51 76*4882a593Smuzhiyun #define CLK_I2C2 52 77*4882a593Smuzhiyun #define CLK_I2C3 53 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define CLK_SPI0 54 80*4882a593Smuzhiyun #define CLK_SPI1 55 81*4882a593Smuzhiyun #define CLK_SPI2 56 82*4882a593Smuzhiyun #define CLK_SPI3 57 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define CLK_USB3_480MPLL0 58 85*4882a593Smuzhiyun #define CLK_USB3_480MPHY0 59 86*4882a593Smuzhiyun #define CLK_USB3_5GPHY 60 87*4882a593Smuzhiyun #define CLK_USB3_CCE 61 88*4882a593Smuzhiyun #define CLK_USB3_MAC 62 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define CLK_LCD 63 91*4882a593Smuzhiyun #define CLK_HDMI_AUDIO 64 92*4882a593Smuzhiyun #define CLK_I2SRX 65 93*4882a593Smuzhiyun #define CLK_I2STX 66 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CLK_SENSOR0 67 96*4882a593Smuzhiyun #define CLK_SENSOR1 68 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CLK_HDMI_DEV 69 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define CLK_ETHERNET 70 101*4882a593Smuzhiyun #define CLK_RMII_REF 71 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CLK_USB2H0_PLLEN 72 104*4882a593Smuzhiyun #define CLK_USB2H0_PHY 73 105*4882a593Smuzhiyun #define CLK_USB2H0_CCE 74 106*4882a593Smuzhiyun #define CLK_USB2H1_PLLEN 75 107*4882a593Smuzhiyun #define CLK_USB2H1_PHY 76 108*4882a593Smuzhiyun #define CLK_USB2H1_CCE 77 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define CLK_TVOUT 78 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CLK_THERMAL_SENSOR 79 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define CLK_IRC_SWITCH 80 115*4882a593Smuzhiyun #define CLK_PCM1 81 116*4882a593Smuzhiyun #define CLK_NR_CLKS (CLK_PCM1 + 1) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_S700_H */ 119