1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree binding constants for Actions Semi S500 Clock Management Unit 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Actions Semi Inc. 6*4882a593Smuzhiyun * Copyright (c) 2018 LSI-TEC - Caninos Loucos 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_S500_CMU_H 10*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_S500_CMU_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_NONE 0 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* fixed rate clocks */ 15*4882a593Smuzhiyun #define CLK_LOSC 1 16*4882a593Smuzhiyun #define CLK_HOSC 2 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* pll clocks */ 19*4882a593Smuzhiyun #define CLK_CORE_PLL 3 20*4882a593Smuzhiyun #define CLK_DEV_PLL 4 21*4882a593Smuzhiyun #define CLK_DDR_PLL 5 22*4882a593Smuzhiyun #define CLK_NAND_PLL 6 23*4882a593Smuzhiyun #define CLK_DISPLAY_PLL 7 24*4882a593Smuzhiyun #define CLK_ETHERNET_PLL 8 25*4882a593Smuzhiyun #define CLK_AUDIO_PLL 9 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* system clock */ 28*4882a593Smuzhiyun #define CLK_DEV 10 29*4882a593Smuzhiyun #define CLK_H 11 30*4882a593Smuzhiyun #define CLK_AHBPREDIV 12 31*4882a593Smuzhiyun #define CLK_AHB 13 32*4882a593Smuzhiyun #define CLK_DE 14 33*4882a593Smuzhiyun #define CLK_BISP 15 34*4882a593Smuzhiyun #define CLK_VCE 16 35*4882a593Smuzhiyun #define CLK_VDE 17 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* peripheral device clock */ 38*4882a593Smuzhiyun #define CLK_TIMER 18 39*4882a593Smuzhiyun #define CLK_I2C0 19 40*4882a593Smuzhiyun #define CLK_I2C1 20 41*4882a593Smuzhiyun #define CLK_I2C2 21 42*4882a593Smuzhiyun #define CLK_I2C3 22 43*4882a593Smuzhiyun #define CLK_PWM0 23 44*4882a593Smuzhiyun #define CLK_PWM1 24 45*4882a593Smuzhiyun #define CLK_PWM2 25 46*4882a593Smuzhiyun #define CLK_PWM3 26 47*4882a593Smuzhiyun #define CLK_PWM4 27 48*4882a593Smuzhiyun #define CLK_PWM5 28 49*4882a593Smuzhiyun #define CLK_SD0 29 50*4882a593Smuzhiyun #define CLK_SD1 30 51*4882a593Smuzhiyun #define CLK_SD2 31 52*4882a593Smuzhiyun #define CLK_SENSOR0 32 53*4882a593Smuzhiyun #define CLK_SENSOR1 33 54*4882a593Smuzhiyun #define CLK_SPI0 34 55*4882a593Smuzhiyun #define CLK_SPI1 35 56*4882a593Smuzhiyun #define CLK_SPI2 36 57*4882a593Smuzhiyun #define CLK_SPI3 37 58*4882a593Smuzhiyun #define CLK_UART0 38 59*4882a593Smuzhiyun #define CLK_UART1 39 60*4882a593Smuzhiyun #define CLK_UART2 40 61*4882a593Smuzhiyun #define CLK_UART3 41 62*4882a593Smuzhiyun #define CLK_UART4 42 63*4882a593Smuzhiyun #define CLK_UART5 43 64*4882a593Smuzhiyun #define CLK_UART6 44 65*4882a593Smuzhiyun #define CLK_DE1 45 66*4882a593Smuzhiyun #define CLK_DE2 46 67*4882a593Smuzhiyun #define CLK_I2SRX 47 68*4882a593Smuzhiyun #define CLK_I2STX 48 69*4882a593Smuzhiyun #define CLK_HDMI_AUDIO 49 70*4882a593Smuzhiyun #define CLK_HDMI 50 71*4882a593Smuzhiyun #define CLK_SPDIF 51 72*4882a593Smuzhiyun #define CLK_NAND 52 73*4882a593Smuzhiyun #define CLK_ECC 53 74*4882a593Smuzhiyun #define CLK_RMII_REF 54 75*4882a593Smuzhiyun #define CLK_GPIO 55 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* system clock (part 2) */ 78*4882a593Smuzhiyun #define CLK_APB 56 79*4882a593Smuzhiyun #define CLK_DMAC 57 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define CLK_NR_CLKS (CLK_DMAC + 1) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ 84