1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree defines for Lochnagar clocking 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6*4882a593Smuzhiyun * Cirrus Logic International Semiconductor Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef DT_BINDINGS_CLK_LOCHNAGAR_H 12*4882a593Smuzhiyun #define DT_BINDINGS_CLK_LOCHNAGAR_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define LOCHNAGAR_CDC_MCLK1 0 15*4882a593Smuzhiyun #define LOCHNAGAR_CDC_MCLK2 1 16*4882a593Smuzhiyun #define LOCHNAGAR_DSP_CLKIN 2 17*4882a593Smuzhiyun #define LOCHNAGAR_GF_CLKOUT1 3 18*4882a593Smuzhiyun #define LOCHNAGAR_GF_CLKOUT2 4 19*4882a593Smuzhiyun #define LOCHNAGAR_PSIA1_MCLK 5 20*4882a593Smuzhiyun #define LOCHNAGAR_PSIA2_MCLK 6 21*4882a593Smuzhiyun #define LOCHNAGAR_SPDIF_MCLK 7 22*4882a593Smuzhiyun #define LOCHNAGAR_ADAT_MCLK 8 23*4882a593Smuzhiyun #define LOCHNAGAR_SOUNDCARD_MCLK 9 24*4882a593Smuzhiyun #define LOCHNAGAR_SPDIF_CLKOUT 10 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif 27