1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3*4882a593Smuzhiyun * All Rights Reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 6*4882a593Smuzhiyun * copy of this software and associated documentation files (the 7*4882a593Smuzhiyun * "Software"), to deal in the Software without restriction, including 8*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish, 9*4882a593Smuzhiyun * distribute, sub license, and/or sell copies of the Software, and to 10*4882a593Smuzhiyun * permit persons to whom the Software is furnished to do so, subject to 11*4882a593Smuzhiyun * the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the 14*4882a593Smuzhiyun * next paragraph) shall be included in all copies or substantial portions 15*4882a593Smuzhiyun * of the Software. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18*4882a593Smuzhiyun * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20*4882a593Smuzhiyun * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21*4882a593Smuzhiyun * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22*4882a593Smuzhiyun * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23*4882a593Smuzhiyun * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #ifndef _I915_DRM_H_ 27*4882a593Smuzhiyun #define _I915_DRM_H_ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #include <drm/i915_pciids.h> 30*4882a593Smuzhiyun #include <uapi/drm/i915_drm.h> 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* For use by IPS driver */ 33*4882a593Smuzhiyun unsigned long i915_read_mch_val(void); 34*4882a593Smuzhiyun bool i915_gpu_raise(void); 35*4882a593Smuzhiyun bool i915_gpu_lower(void); 36*4882a593Smuzhiyun bool i915_gpu_busy(void); 37*4882a593Smuzhiyun bool i915_gpu_turbo_disable(void); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Exported from arch/x86/kernel/early-quirks.c */ 40*4882a593Smuzhiyun extern struct resource intel_graphics_stolen_res; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * The Bridge device's PCI config space has information about the 44*4882a593Smuzhiyun * fb aperture size and the amount of pre-reserved memory. 45*4882a593Smuzhiyun * This is all handled in the intel-gtt.ko module. i915.ko only 46*4882a593Smuzhiyun * cares about the vga bit for the vga rbiter. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define INTEL_GMCH_CTRL 0x52 49*4882a593Smuzhiyun #define INTEL_GMCH_VGA_DISABLE (1 << 1) 50*4882a593Smuzhiyun #define SNB_GMCH_CTRL 0x50 51*4882a593Smuzhiyun #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ 52*4882a593Smuzhiyun #define SNB_GMCH_GGMS_MASK 0x3 53*4882a593Smuzhiyun #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ 54*4882a593Smuzhiyun #define SNB_GMCH_GMS_MASK 0x1f 55*4882a593Smuzhiyun #define BDW_GMCH_GGMS_SHIFT 6 56*4882a593Smuzhiyun #define BDW_GMCH_GGMS_MASK 0x3 57*4882a593Smuzhiyun #define BDW_GMCH_GMS_SHIFT 8 58*4882a593Smuzhiyun #define BDW_GMCH_GMS_MASK 0xff 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define I830_GMCH_CTRL 0x52 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define I830_GMCH_GMS_MASK 0x70 63*4882a593Smuzhiyun #define I830_GMCH_GMS_LOCAL 0x10 64*4882a593Smuzhiyun #define I830_GMCH_GMS_STOLEN_512 0x20 65*4882a593Smuzhiyun #define I830_GMCH_GMS_STOLEN_1024 0x30 66*4882a593Smuzhiyun #define I830_GMCH_GMS_STOLEN_8192 0x40 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define I855_GMCH_GMS_MASK 0xF0 69*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_0M 0x0 70*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 71*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 72*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 73*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 74*4882a593Smuzhiyun #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 75*4882a593Smuzhiyun #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 76*4882a593Smuzhiyun #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 77*4882a593Smuzhiyun #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 78*4882a593Smuzhiyun #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 79*4882a593Smuzhiyun #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 80*4882a593Smuzhiyun #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 81*4882a593Smuzhiyun #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 82*4882a593Smuzhiyun #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define I830_DRB3 0x63 85*4882a593Smuzhiyun #define I85X_DRB3 0x43 86*4882a593Smuzhiyun #define I865_TOUD 0xc4 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define I830_ESMRAMC 0x91 89*4882a593Smuzhiyun #define I845_ESMRAMC 0x9e 90*4882a593Smuzhiyun #define I85X_ESMRAMC 0x61 91*4882a593Smuzhiyun #define TSEG_ENABLE (1 << 0) 92*4882a593Smuzhiyun #define I830_TSEG_SIZE_512K (0 << 1) 93*4882a593Smuzhiyun #define I830_TSEG_SIZE_1M (1 << 1) 94*4882a593Smuzhiyun #define I845_TSEG_SIZE_MASK (3 << 1) 95*4882a593Smuzhiyun #define I845_TSEG_SIZE_512K (2 << 1) 96*4882a593Smuzhiyun #define I845_TSEG_SIZE_1M (3 << 1) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define INTEL_BSM 0x5c 99*4882a593Smuzhiyun #define INTEL_GEN11_BSM_DW0 0xc0 100*4882a593Smuzhiyun #define INTEL_GEN11_BSM_DW1 0xc4 101*4882a593Smuzhiyun #define INTEL_BSM_MASK (-(1u << 20)) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* _I915_DRM_H_ */ 104